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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / f62168d3c3d9bc0301dbc3ef9dc6d889ac19412e / . / drivers / gpio / intel_gpio.c
blob: 4bf1c9ddc4e7057544d287b9aa08f41612955814 [file] [log] [blame]
Simon Glass7e589bc2019-12-06 21:42:54 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Google LLC
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <errno.h>
9#include <fdtdec.h>
10#include <p2sb.h>
11#include <pch.h>
12#include <pci.h>
13#include <syscon.h>
14#include <asm/cpu.h>
15#include <asm/gpio.h>
16#include <asm/intel_pinctrl.h>
17#include <asm/intel_pinctrl_defs.h>
18#include <asm/io.h>
19#include <asm/pci.h>
20#include <asm/arch/gpio.h>
21#include <dt-bindings/gpio/x86-gpio.h>
22
23static int intel_gpio_direction_input(struct udevice *dev, uint offset)
24{
25 struct udevice *pinctrl = dev_get_parent(dev);
26 uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
27
28 pcr_clrsetbits32(pinctrl, config_offset,
29 PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
30 PAD_CFG0_RX_DISABLE,
31 PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE);
32
33 return 0;
34}
35
36static int intel_gpio_direction_output(struct udevice *dev, uint offset,
37 int value)
38{
39 struct udevice *pinctrl = dev_get_parent(dev);
40 uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
41
42 pcr_clrsetbits32(dev, config_offset,
43 PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
44 PAD_CFG0_TX_DISABLE,
45 PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE |
46 (value ? PAD_CFG0_TX_STATE : 0));
47
48 return 0;
49}
50
51static int intel_gpio_get_value(struct udevice *dev, uint offset)
52{
53 struct udevice *pinctrl = dev_get_parent(dev);
54 uint mode, rx_tx;
55 u32 reg;
56
57 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
58 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
59 if (!mode) {
60 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
61 if (rx_tx == PAD_CFG0_TX_DISABLE)
62 return mode & PAD_CFG0_RX_STATE_BIT ? 1 : 0;
63 else if (rx_tx == PAD_CFG0_RX_DISABLE)
64 return mode & PAD_CFG0_TX_STATE_BIT ? 1 : 0;
65 }
66
67 return 0;
68}
69
70static int intel_gpio_set_value(struct udevice *dev, unsigned offset, int value)
71{
72 struct udevice *pinctrl = dev_get_parent(dev);
73 uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
74
75 pcr_clrsetbits32(dev, config_offset, PAD_CFG0_TX_STATE,
76 value ? PAD_CFG0_TX_STATE : 0);
77
78 return 0;
79}
80
81static int intel_gpio_get_function(struct udevice *dev, uint offset)
82{
83 struct udevice *pinctrl = dev_get_parent(dev);
84 uint mode, rx_tx;
85 u32 reg;
86
87 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
88 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
89 if (!mode) {
90 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
91 if (rx_tx == PAD_CFG0_TX_DISABLE)
92 return GPIOF_INPUT;
93 else if (rx_tx == PAD_CFG0_RX_DISABLE)
94 return GPIOF_OUTPUT;
95 }
96
97 return GPIOF_FUNC;
98}
99
100static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
101 struct ofnode_phandle_args *args)
102{
103 struct udevice *pinctrl, *dev;
104 int gpio, ret;
105
106 /*
107 * GPIO numbers are global in the device tree so it doesn't matter
108 * which one is used
109 */
110 gpio = args->args[0];
111 ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);
112 if (ret)
113 return log_msg_ret("bad", ret);
114 device_find_first_child(pinctrl, &dev);
115 if (!dev)
116 return log_msg_ret("no child", -ENOENT);
117 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
118 desc->dev = dev;
119
120 return 0;
121}
122
123static int intel_gpio_probe(struct udevice *dev)
124{
125 return 0;
126}
127
128static int intel_gpio_ofdata_to_platdata(struct udevice *dev)
129{
130 struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
131 struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
132 const struct pad_community *comm = pinctrl_priv->comm;
133
134 upriv->gpio_count = comm->last_pad - comm->first_pad + 1;
135 upriv->bank_name = dev->name;
136
137 return 0;
138}
139
140static const struct dm_gpio_ops gpio_intel_ops = {
141 .direction_input = intel_gpio_direction_input,
142 .direction_output = intel_gpio_direction_output,
143 .get_value = intel_gpio_get_value,
144 .set_value = intel_gpio_set_value,
145 .get_function = intel_gpio_get_function,
146 .xlate = intel_gpio_xlate,
147};
148
149static const struct udevice_id intel_intel_gpio_ids[] = {
150 { .compatible = "intel,gpio" },
151 { }
152};
153
154U_BOOT_DRIVER(gpio_intel) = {
155 .name = "gpio_intel",
156 .id = UCLASS_GPIO,
157 .of_match = intel_intel_gpio_ids,
158 .ops = &gpio_intel_ops,
159 .ofdata_to_platdata = intel_gpio_ofdata_to_platdata,
160 .probe = intel_gpio_probe,
161};