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wdenk5e5f9ed2005-04-13 23:15:10 +00001/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
wdenkb2323ea2005-04-20 09:28:54 +00005 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
wdenk5e5f9ed2005-04-13 23:15:10 +00007 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
29#include <pci.h>
30
wdenkb2323ea2005-04-20 09:28:54 +000031#if defined(CONFIG_MPC5200_DDR)
32#include "mt46v16m16-75.h"
33#else
34#include "mt48lc16m32s2-75.h"
35#endif
36
37#ifndef CFG_RAMBOOT
38static void sdram_start (int hi_addr)
39{
40 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
41
42 /* unlock mode register */
43 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
44 __asm__ volatile ("sync");
45
46 /* precharge all banks */
47 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
48 __asm__ volatile ("sync");
49
50#if SDRAM_DDR
51 /* set mode register: extended mode */
52 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
53 __asm__ volatile ("sync");
54
55 /* set mode register: reset DLL */
56 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
57 __asm__ volatile ("sync");
58#endif
59
60 /* precharge all banks */
61 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
62 __asm__ volatile ("sync");
63
64 /* auto refresh */
65 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
66 __asm__ volatile ("sync");
67
68 /* set mode register */
69 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
70 __asm__ volatile ("sync");
71
72 /* normal operation */
73 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
74 __asm__ volatile ("sync");
75}
76#endif
77
78/*
79 * ATTENTION: Although partially referenced initdram does NOT make real use
80 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
81 * is something else than 0x00000000.
82 */
83
84#if defined(CONFIG_MPC5200)
Becky Bruce9973e3c2008-06-09 16:03:40 -050085phys_size_t initdram (int board_type)
wdenkb2323ea2005-04-20 09:28:54 +000086{
87 ulong dramsize = 0;
88 ulong dramsize2 = 0;
89#ifndef CFG_RAMBOOT
90 ulong test1, test2;
91
92 /* setup SDRAM chip selects */
93 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
94 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
95 __asm__ volatile ("sync");
96
97 /* setup config registers */
98 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
99 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
100 __asm__ volatile ("sync");
101
102#if SDRAM_DDR
103 /* set tap delay */
104 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
105 __asm__ volatile ("sync");
106#endif
107
108 /* find RAM size using SDRAM CS0 only */
109 sdram_start(0);
110 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
111 sdram_start(1);
112 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
113 if (test1 > test2) {
114 sdram_start(0);
115 dramsize = test1;
116 } else {
117 dramsize = test2;
118 }
119
120 /* memory smaller than 1MB is impossible */
121 if (dramsize < (1 << 20)) {
122 dramsize = 0;
123 }
124
125 /* set SDRAM CS0 size according to the amount of RAM found */
126 if (dramsize > 0) {
127 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
128 } else {
129 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
130 }
131
132 /* let SDRAM CS1 start right after CS0 */
133 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
134
135 /* find RAM size using SDRAM CS1 only */
wdenk07cc0992005-05-05 00:04:14 +0000136 if (!dramsize)
wdenka6310922005-04-21 21:10:22 +0000137 sdram_start(0);
138 test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
139 if (!dramsize) {
140 sdram_start(1);
141 test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
142 }
wdenkb2323ea2005-04-20 09:28:54 +0000143 if (test1 > test2) {
144 sdram_start(0);
145 dramsize2 = test1;
146 } else {
147 dramsize2 = test2;
148 }
149
150 /* memory smaller than 1MB is impossible */
151 if (dramsize2 < (1 << 20)) {
152 dramsize2 = 0;
153 }
154
155 /* set SDRAM CS1 size according to the amount of RAM found */
156 if (dramsize2 > 0) {
157 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
158 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
159 } else {
160 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
161 }
162
163#else /* CFG_RAMBOOT */
164
165 /* retrieve size of memory connected to SDRAM CS0 */
166 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
167 if (dramsize >= 0x13) {
168 dramsize = (1 << (dramsize - 0x13)) << 20;
169 } else {
170 dramsize = 0;
171 }
172
173 /* retrieve size of memory connected to SDRAM CS1 */
174 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
175 if (dramsize2 >= 0x13) {
176 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
177 } else {
178 dramsize2 = 0;
179 }
180
181#endif /* CFG_RAMBOOT */
182
183 return dramsize + dramsize2;
184}
185
186#elif defined(CONFIG_MGT5100)
187
Becky Bruce9973e3c2008-06-09 16:03:40 -0500188phys_size_t initdram (int board_type)
wdenk5e5f9ed2005-04-13 23:15:10 +0000189{
190 ulong dramsize = 0;
191#ifndef CFG_RAMBOOT
wdenkb2323ea2005-04-20 09:28:54 +0000192 ulong test1, test2;
wdenk5e5f9ed2005-04-13 23:15:10 +0000193
wdenkb2323ea2005-04-20 09:28:54 +0000194 /* setup and enable SDRAM chip selects */
195 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
196 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
197 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
198 __asm__ volatile ("sync");
wdenk5e5f9ed2005-04-13 23:15:10 +0000199
200 /* setup config registers */
wdenkb2323ea2005-04-20 09:28:54 +0000201 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
202 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
wdenk5e5f9ed2005-04-13 23:15:10 +0000203
wdenkb2323ea2005-04-20 09:28:54 +0000204 /* address select register */
205 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
206 __asm__ volatile ("sync");
207
208 /* find RAM size */
209 sdram_start(0);
210 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
211 sdram_start(1);
212 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
213 if (test1 > test2) {
214 sdram_start(0);
215 dramsize = test1;
216 } else {
217 dramsize = test2;
218 }
219
220 /* set SDRAM end address according to size */
221 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
222
223#else /* CFG_RAMBOOT */
224
225 /* Retrieve amount of SDRAM available */
226 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
wdenk5e5f9ed2005-04-13 23:15:10 +0000227
228#endif /* CFG_RAMBOOT */
229
wdenk5e5f9ed2005-04-13 23:15:10 +0000230 return dramsize;
231}
232
wdenkb2323ea2005-04-20 09:28:54 +0000233#else
234#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
235#endif
236
wdenk5e5f9ed2005-04-13 23:15:10 +0000237int checkboard (void)
238{
239 puts ("Board: CANMB\n");
240 return 0;
241}
242
243int board_early_init_r (void)
244{
245 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
246 *(vu_long *)MPC5XXX_BOOTCS_START =
247 *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
248 *(vu_long *)MPC5XXX_BOOTCS_STOP =
249 *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
250 return 0;
251}