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Stefan Roeseb765ffb2007-06-15 08:18:01 +02001/*
2 * (C) Copyright 2006
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02003 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
Stefan Roeseb765ffb2007-06-15 08:18:01 +02004 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02005 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
6 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
7 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
Stefan Roeseb765ffb2007-06-15 08:18:01 +02008 *
Stefan Roese7e4a0d22008-03-19 09:36:47 +01009 * (C) Copyright 2007-2008
Stefan Roeseb765ffb2007-06-15 08:18:01 +020010 * Stefan Roese, DENX Software Engineering, sr@denx.de.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28/* define DEBUG for debugging output (obviously ;-)) */
29#if 0
30#define DEBUG
31#endif
32
33#include <common.h>
34#include <asm/processor.h>
35#include <asm/mmu.h>
36#include <asm/io.h>
Stefan Roese135846d2008-04-29 13:36:51 +020037#include <asm/cache.h>
Stefan Roeseb765ffb2007-06-15 08:18:01 +020038#include <ppc440.h>
Stefan Roese7e4a0d22008-03-19 09:36:47 +010039#include <watchdog.h>
Stefan Roeseb765ffb2007-06-15 08:18:01 +020040
Stefan Roeseb765ffb2007-06-15 08:18:01 +020041/*
42 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
43 * region. Right now the cache should still be disabled in U-Boot because of the
44 * EMAC driver, that need it's buffer descriptor to be located in non cached
45 * memory.
46 *
47 * If at some time this restriction doesn't apply anymore, just define
48 * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
49 * everything correctly.
50 */
51#ifdef CFG_ENABLE_SDRAM_CACHE
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020052#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020053#else
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020054#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020055#endif
56
Larry Johnsonef16fcc2007-12-30 01:01:32 -050057/*-----------------------------------------------------------------------------+
58 * Prototypes
59 *-----------------------------------------------------------------------------*/
60extern int denali_wait_for_dlllock(void);
61extern void denali_core_search_data_eye(void);
62extern void dcbz_area(u32 start_address, u32 num_bytes);
Stefan Roeseb765ffb2007-06-15 08:18:01 +020063
Stefan Roeseb765ffb2007-06-15 08:18:01 +020064static u32 is_ecc_enabled(void)
65{
66 u32 val;
67
68 mfsdram(DDR0_22, val);
69 val &= DDR0_22_CTRL_RAW_MASK;
70 if (val)
71 return 1;
72 else
73 return 0;
74}
75
76void board_add_ram_info(int use_default)
77{
Stefan Roese087dfdb2007-10-21 08:12:41 +020078 PPC4xx_SYS_INFO board_cfg;
Stefan Roeseb765ffb2007-06-15 08:18:01 +020079 u32 val;
80
81 if (is_ecc_enabled())
82 puts(" (ECC");
83 else
84 puts(" (ECC not");
85
86 get_sys_info(&board_cfg);
Stefan Roeseb0021442008-07-10 09:58:06 +020087 printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
Stefan Roeseb765ffb2007-06-15 08:18:01 +020088
89 mfsdram(DDR0_03, val);
90 val = DDR0_03_CASLAT_DECODE(val);
91 printf(", CL%d)", val);
92}
Stefan Roeseb765ffb2007-06-15 08:18:01 +020093
Stefan Roeseb765ffb2007-06-15 08:18:01 +020094#ifdef CONFIG_DDR_ECC
95static void wait_ddr_idle(void)
96{
97 /*
98 * Controller idle status cannot be determined for Denali
99 * DDR2 code. Just return here.
100 */
101}
102
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200103static void program_ecc(u32 start_address,
104 u32 num_bytes,
105 u32 tlb_word2_i_value)
106{
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200107 u32 val;
Stefan Roese7e4a0d22008-03-19 09:36:47 +0100108 u32 current_addr = start_address;
Stefan Roese135846d2008-04-29 13:36:51 +0200109 u32 size;
Stefan Roese7e4a0d22008-03-19 09:36:47 +0100110 int bytes_remaining;
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200111
112 sync();
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200113 wait_ddr_idle();
114
Stefan Roese7e4a0d22008-03-19 09:36:47 +0100115 /*
116 * Because of 440EPx errata CHIP 11, we don't touch the last 256
117 * bytes of SDRAM.
118 */
119 bytes_remaining = num_bytes - CFG_MEM_TOP_HIDE;
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200120
Stefan Roese7e4a0d22008-03-19 09:36:47 +0100121 /*
122 * We have to write the ECC bytes by zeroing and flushing in smaller
123 * steps, since the whole 256MByte takes too long for the external
124 * watchdog.
125 */
126 while (bytes_remaining > 0) {
Stefan Roese135846d2008-04-29 13:36:51 +0200127 size = min((64 << 20), bytes_remaining);
128
129 /* Write zero's to SDRAM */
130 dcbz_area(current_addr, size);
131
132 /* Write modified dcache lines back to memory */
133 clean_dcache_range(current_addr, current_addr + size);
134
Stefan Roese7e4a0d22008-03-19 09:36:47 +0100135 current_addr += 64 << 20;
136 bytes_remaining -= 64 << 20;
137 WATCHDOG_RESET();
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200138 }
139
140 sync();
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200141 wait_ddr_idle();
142
143 /* Clear error status */
144 mfsdram(DDR0_00, val);
145 mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
146
147 /* Set 'int_mask' parameter to functionnal value */
148 mfsdram(DDR0_01, val);
149 mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
150
151 sync();
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200152 wait_ddr_idle();
153}
154#endif
155
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200156/*************************************************************************
157 *
158 * initdram -- 440EPx's DDR controller is a DENALI Core
159 *
160 ************************************************************************/
Becky Bruce9973e3c2008-06-09 16:03:40 -0500161phys_size_t initdram (int board_type)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200162{
Stefan Roese04e6c382007-07-04 10:06:30 +0200163#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
164 /* CL=3 */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200165 mtsdram(DDR0_02, 0x00000000);
166
167 mtsdram(DDR0_00, 0x0000190A);
168 mtsdram(DDR0_01, 0x01000000);
169 mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
170
171 mtsdram(DDR0_04, 0x0A030300);
172 mtsdram(DDR0_05, 0x02020308);
173 mtsdram(DDR0_06, 0x0103C812);
174 mtsdram(DDR0_07, 0x00090100);
175 mtsdram(DDR0_08, 0x02c80001);
176 mtsdram(DDR0_09, 0x00011D5F);
177 mtsdram(DDR0_10, 0x00000300);
178 mtsdram(DDR0_11, 0x000CC800);
179 mtsdram(DDR0_12, 0x00000003);
180 mtsdram(DDR0_14, 0x00000000);
181 mtsdram(DDR0_17, 0x1e000000);
182 mtsdram(DDR0_18, 0x1e1e1e1e);
183 mtsdram(DDR0_19, 0x1e1e1e1e);
184 mtsdram(DDR0_20, 0x0B0B0B0B);
185 mtsdram(DDR0_21, 0x0B0B0B0B);
186#ifdef CONFIG_DDR_ECC
187 mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
188#else
189 mtsdram(DDR0_22, 0x00267F0B);
190#endif
191
192 mtsdram(DDR0_23, 0x01000000);
193 mtsdram(DDR0_24, 0x01010001);
194
195 mtsdram(DDR0_26, 0x2D93028A);
196 mtsdram(DDR0_27, 0x0784682B);
197
198 mtsdram(DDR0_28, 0x00000080);
199 mtsdram(DDR0_31, 0x00000000);
200 mtsdram(DDR0_42, 0x01000006);
201
202 mtsdram(DDR0_43, 0x030A0200);
203 mtsdram(DDR0_44, 0x00000003);
204 mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
Stefan Roese04e6c382007-07-04 10:06:30 +0200205#else
206 /* CL=4 */
207 mtsdram(DDR0_02, 0x00000000);
208
209 mtsdram(DDR0_00, 0x0000190A);
210 mtsdram(DDR0_01, 0x01000000);
211 mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
212
213 mtsdram(DDR0_04, 0x0B030300);
214 mtsdram(DDR0_05, 0x02020308);
215 mtsdram(DDR0_06, 0x0003C812);
216 mtsdram(DDR0_07, 0x00090100);
217 mtsdram(DDR0_08, 0x03c80001);
218 mtsdram(DDR0_09, 0x00011D5F);
219 mtsdram(DDR0_10, 0x00000300);
220 mtsdram(DDR0_11, 0x000CC800);
221 mtsdram(DDR0_12, 0x00000003);
222 mtsdram(DDR0_14, 0x00000000);
223 mtsdram(DDR0_17, 0x1e000000);
224 mtsdram(DDR0_18, 0x1e1e1e1e);
225 mtsdram(DDR0_19, 0x1e1e1e1e);
226 mtsdram(DDR0_20, 0x0B0B0B0B);
227 mtsdram(DDR0_21, 0x0B0B0B0B);
228#ifdef CONFIG_DDR_ECC
229 mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
230#else
231 mtsdram(DDR0_22, 0x00267F0B);
232#endif
233
234 mtsdram(DDR0_23, 0x01000000);
235 mtsdram(DDR0_24, 0x01010001);
236
237 mtsdram(DDR0_26, 0x2D93028A);
238 mtsdram(DDR0_27, 0x0784682B);
239
240 mtsdram(DDR0_28, 0x00000080);
241 mtsdram(DDR0_31, 0x00000000);
242 mtsdram(DDR0_42, 0x01000008);
243
244 mtsdram(DDR0_43, 0x050A0200);
245 mtsdram(DDR0_44, 0x00000005);
246 mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
247#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200248
Larry Johnsonef16fcc2007-12-30 01:01:32 -0500249 denali_wait_for_dlllock();
250
251#if defined(CONFIG_DDR_DATA_EYE)
252 /* -----------------------------------------------------------+
253 * Perform data eye search if requested.
254 * ----------------------------------------------------------*/
255 program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
256 TLB_WORD2_I_ENABLE);
257 denali_core_search_data_eye();
258 remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
259#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200260
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200261 /*
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200262 * Program tlb entries for this size (dynamic)
263 */
Larry Johnsonef16fcc2007-12-30 01:01:32 -0500264 program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
265 MY_TLB_WORD2_I_ENABLE);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200266
267 /*
268 * Setup 2nd TLB with same physical address but different virtual address
269 * with cache enabled. This is done for fast ECC generation.
270 */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200271 program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200272
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200273#ifdef CONFIG_DDR_ECC
274 /*
275 * If ECC is enabled, initialize the parity bits.
276 */
277 program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
278#endif
279
Stefan Roeseea9f6bc2007-07-31 08:37:01 +0200280 /*
281 * Clear possible errors resulting from data-eye-search.
282 * If not done, then we could get an interrupt later on when
283 * exceptions are enabled.
284 */
285 set_mcsr(get_mcsr());
286
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200287 return (CFG_MBYTES_SDRAM << 20);
288}