| Paul Burton | b2b135d | 2016-09-21 11:18:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * MIPS Coherence Manager (CM) Initialisation |
| 3 | * |
| 4 | * Copyright (c) 2016 Imagination Technologies Ltd. |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #include <asm/addrspace.h> |
| 10 | #include <asm/asm.h> |
| 11 | #include <asm/cm.h> |
| 12 | #include <asm/mipsregs.h> |
| 13 | #include <asm/regdef.h> |
| 14 | |
| 15 | LEAF(mips_cm_map) |
| 16 | /* Config3 must exist for a CM to be present */ |
| 17 | mfc0 t0, CP0_CONFIG, 1 |
| 18 | bgez t0, 2f |
| 19 | mfc0 t0, CP0_CONFIG, 2 |
| 20 | bgez t0, 2f |
| 21 | |
| 22 | /* Check Config3.CMGCR to determine CM presence */ |
| 23 | mfc0 t0, CP0_CONFIG, 3 |
| 24 | and t0, t0, MIPS_CONF3_CMGCR |
| 25 | beqz t0, 2f |
| 26 | |
| 27 | /* Find the current physical GCR base address */ |
| 28 | 1: MFC0 t0, CP0_CMGCRBASE |
| 29 | PTR_SLL t0, t0, 4 |
| 30 | |
| 31 | /* If the GCRs are where we want, we're done */ |
| 32 | PTR_LI t1, CONFIG_MIPS_CM_BASE |
| 33 | beq t0, t1, 2f |
| 34 | |
| 35 | /* Move the GCRs to our configured base address */ |
| 36 | PTR_LI t2, CKSEG1 |
| 37 | PTR_ADDU t0, t0, t2 |
| 38 | sw zero, GCR_BASE_UPPER(t0) |
| 39 | sw t1, GCR_BASE(t0) |
| 40 | |
| 41 | /* Re-check the GCR base */ |
| 42 | b 1b |
| 43 | |
| 44 | 2: jr ra |
| 45 | END(mips_cm_map) |