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Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00001/*
2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
Paul Burtonbaf37f02013-11-08 11:18:50 +00003 * Copyright (C) 2013 Imagination Technologies
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00004 *
Tom Rini0b179982013-07-24 09:34:30 -04005 * SPDX-License-Identifier: GPL-2.0
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00006 */
7
8#include <common.h>
Gabor Juhosf1957492013-05-22 03:57:44 +00009#include <netdev.h>
Paul Burton81f98bb2013-11-08 11:18:57 +000010#include <pci.h>
Paul Burtonbaf37f02013-11-08 11:18:50 +000011#include <pci_gt64120.h>
12#include <pci_msc01.h>
Paul Burton3ced12a2013-11-08 11:18:55 +000013#include <rtc.h>
Paul Burtonbaf37f02013-11-08 11:18:50 +000014#include <serial.h>
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000015
Gabor Juhosfeaa6062013-05-22 03:57:42 +000016#include <asm/addrspace.h>
Gabor Juhos01564312013-05-22 03:57:38 +000017#include <asm/io.h>
18#include <asm/malta.h>
19
Paul Burtona257f622013-11-08 11:18:49 +000020#include "superio.h"
21
Paul Burtonbaf37f02013-11-08 11:18:50 +000022enum core_card {
23 CORE_UNKNOWN,
24 CORE_LV,
25 CORE_FPGA6,
26};
27
28enum sys_con {
29 SYSCON_UNKNOWN,
30 SYSCON_GT64120,
31 SYSCON_MSC01,
32};
33
Paul Burtone0ada632013-11-08 11:18:51 +000034static void malta_lcd_puts(const char *str)
35{
36 int i;
37 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
38
39 /* print up to 8 characters of the string */
40 for (i = 0; i < min(strlen(str), 8); i++) {
41 __raw_writel(str[i], reg);
42 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
43 }
44
45 /* fill the rest of the display with spaces */
46 for (; i < 8; i++) {
47 __raw_writel(' ', reg);
48 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
49 }
50}
51
Paul Burtonbaf37f02013-11-08 11:18:50 +000052static enum core_card malta_core_card(void)
53{
54 u32 corid, rev;
55
56 rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
57 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
58
59 switch (corid) {
60 case MALTA_REVISION_CORID_CORE_LV:
61 return CORE_LV;
62
63 case MALTA_REVISION_CORID_CORE_FPGA6:
64 return CORE_FPGA6;
65
66 default:
67 return CORE_UNKNOWN;
68 }
69}
70
71static enum sys_con malta_sys_con(void)
72{
73 switch (malta_core_card()) {
74 case CORE_LV:
75 return SYSCON_GT64120;
76
77 case CORE_FPGA6:
78 return SYSCON_MSC01;
79
80 default:
81 return SYSCON_UNKNOWN;
82 }
83}
84
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000085phys_size_t initdram(int board_type)
86{
87 return CONFIG_SYS_MEM_SIZE;
88}
89
90int checkboard(void)
91{
Paul Burtonbaf37f02013-11-08 11:18:50 +000092 enum core_card core;
93
Paul Burtone0ada632013-11-08 11:18:51 +000094 malta_lcd_puts("U-boot");
Paul Burtonbaf37f02013-11-08 11:18:50 +000095 puts("Board: MIPS Malta");
96
97 core = malta_core_card();
98 switch (core) {
99 case CORE_LV:
100 puts(" CoreLV");
101 break;
102
103 case CORE_FPGA6:
104 puts(" CoreFPGA6");
105 break;
106
107 default:
108 puts(" CoreUnknown");
109 }
110
111 putc('\n');
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +0000112 return 0;
113}
Gabor Juhos01564312013-05-22 03:57:38 +0000114
Gabor Juhosf1957492013-05-22 03:57:44 +0000115int board_eth_init(bd_t *bis)
116{
117 return pci_eth_init(bis);
118}
119
Gabor Juhos01564312013-05-22 03:57:38 +0000120void _machine_restart(void)
121{
122 void __iomem *reset_base;
123
124 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
125 __raw_writel(GORESET, reset_base);
126}
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000127
Paul Burtona257f622013-11-08 11:18:49 +0000128int board_early_init_f(void)
129{
Paul Burtonbaf37f02013-11-08 11:18:50 +0000130 void *io_base;
131
132 /* choose correct PCI I/O base */
133 switch (malta_sys_con()) {
134 case SYSCON_GT64120:
135 io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
136 break;
137
138 case SYSCON_MSC01:
139 io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
140 break;
141
142 default:
143 return -1;
144 }
145
Paul Burtona257f622013-11-08 11:18:49 +0000146 /* setup FDC37M817 super I/O controller */
Paul Burtonbaf37f02013-11-08 11:18:50 +0000147 malta_superio_init(io_base);
Paul Burtona257f622013-11-08 11:18:49 +0000148
149 return 0;
150}
151
Paul Burton3ced12a2013-11-08 11:18:55 +0000152int misc_init_r(void)
153{
154 rtc_reset();
155
156 return 0;
157}
158
Paul Burtonbaf37f02013-11-08 11:18:50 +0000159struct serial_device *default_serial_console(void)
160{
161 switch (malta_sys_con()) {
162 case SYSCON_GT64120:
163 return &eserial1_device;
164
165 default:
166 case SYSCON_MSC01:
167 return &eserial2_device;
168 }
169}
170
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000171void pci_init_board(void)
172{
Paul Burton81f98bb2013-11-08 11:18:57 +0000173 pci_dev_t bdf;
Paul Burtonbea12b72013-11-26 17:45:27 +0000174 u32 val32;
175 u8 val8;
Paul Burton81f98bb2013-11-08 11:18:57 +0000176
Paul Burtonbaf37f02013-11-08 11:18:50 +0000177 switch (malta_sys_con()) {
178 case SYSCON_GT64120:
179 set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000180
Paul Burtonbaf37f02013-11-08 11:18:50 +0000181 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
182 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
183 0x10000000, 0x10000000, 128 * 1024 * 1024,
184 0x00000000, 0x00000000, 0x20000);
185 break;
186
187 default:
188 case SYSCON_MSC01:
189 set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));
190
191 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
192 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
193 MALTA_MSC01_PCIMEM_MAP,
194 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
195 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
196 0x00000000, MALTA_MSC01_PCIIO_SIZE);
197 break;
198 }
Paul Burton81f98bb2013-11-08 11:18:57 +0000199
200 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
201 PCI_DEVICE_ID_INTEL_82371AB_0, 0);
202 if (bdf == -1)
203 panic("Failed to find PIIX4 PCI bridge\n");
204
205 /* setup PCI interrupt routing */
206 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
207 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
208 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
209 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
Paul Burtonbea12b72013-11-26 17:45:27 +0000210
211 /* mux SERIRQ onto SERIRQ pin */
212 pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
213 val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
214 pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
215
216 /* enable SERIRQ - Linux currently depends upon this */
217 pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
218 val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
219 pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000220}