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wdenkc6097192002-11-03 00:24:07 +00001/*
stroesea20b27a2004-12-16 18:05:42 +00002 * (C) Copyright 2001-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
wdenkc6097192002-11-03 00:24:07 +000038#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
wdenkc837dcb2004-01-20 23:12:12 +000039#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020040#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
wdenkc6097192002-11-03 00:24:07 +000041
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050043#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
wdenkc6097192002-11-03 00:24:07 +000044
stroesea20b27a2004-12-16 18:05:42 +000045#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000046
47#define CONFIG_BAUDRATE 9600
48#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
49
wdenkc6097192002-11-03 00:24:07 +000050#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000051#undef CONFIG_BOOTCOMMAND
52
53#define CONFIG_PREBOOT /* enable preboot variable */
wdenkc6097192002-11-03 00:24:07 +000054
55#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +000057
Ben Warren96e21f82008-10-27 23:50:15 -070058#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +000059#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000060#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000061#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020062#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
63
64#define CONFIG_NET_MULTI 1
65#undef CONFIG_HAS_ETH1
wdenkc6097192002-11-03 00:24:07 +000066
67#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
68
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050069/*
70 * BOOTP options
71 */
72#define CONFIG_BOOTP_SUBNETMASK
73#define CONFIG_BOOTP_GATEWAY
74#define CONFIG_BOOTP_HOSTNAME
75#define CONFIG_BOOTP_BOOTPATH
76#define CONFIG_BOOTP_DNS
77#define CONFIG_BOOTP_DNS2
78#define CONFIG_BOOTP_SEND_HOSTNAME
stroese9919f132003-05-23 11:38:22 +000079
wdenkc6097192002-11-03 00:24:07 +000080
Jon Loeliger49cf7e82007-07-05 19:52:35 -050081/*
82 * Command line configuration.
83 */
84#include <config_cmd_default.h>
85
86#define CONFIG_CMD_DHCP
87#define CONFIG_CMD_PCI
88#define CONFIG_CMD_IRQ
89#define CONFIG_CMD_IDE
90#define CONFIG_CMD_FAT
91#define CONFIG_CMD_ELF
92#define CONFIG_CMD_DATE
Jon Loeliger49cf7e82007-07-05 19:52:35 -050093#define CONFIG_CMD_I2C
94#define CONFIG_CMD_MII
95#define CONFIG_CMD_PING
96#define CONFIG_CMD_BSP
97#define CONFIG_CMD_EEPROM
98
wdenkc6097192002-11-03 00:24:07 +000099#define CONFIG_MAC_PARTITION
100#define CONFIG_DOS_PARTITION
101
stroesea20b27a2004-12-16 18:05:42 +0000102#define CONFIG_SUPPORT_VFAT
103
wdenkc837dcb2004-01-20 23:12:12 +0000104#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +0000105
wdenkc837dcb2004-01-20 23:12:12 +0000106#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +0000107
108/*
109 * Miscellaneous configurable options
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_LONGHELP /* undef to save memory */
112#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkc6097192002-11-03 00:24:07 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
115#ifdef CONFIG_SYS_HUSH_PARSER
116#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkc6097192002-11-03 00:24:07 +0000117#endif
118
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500119#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000121#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000123#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
125#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
126#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
wdenkc6097192002-11-03 00:24:07 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +0000131
stroesea20b27a2004-12-16 18:05:42 +0000132#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
135#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000139
140/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000142 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
143 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
146#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000149
Matthias Fuchsac53ee82008-09-05 15:34:04 +0200150#define CONFIG_CMDLINE_EDITING /* add command line history */
151
stroesea20b27a2004-12-16 18:05:42 +0000152#define CONFIG_LOOPW 1 /* enable loopw command */
153
wdenkc6097192002-11-03 00:24:07 +0000154#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
155
wdenkc837dcb2004-01-20 23:12:12 +0000156#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese9e7d5eb2003-04-04 16:48:07 +0000157
Matthias Fuchs75511b42009-02-20 10:19:14 +0100158#define CONFIG_AUTOBOOT_KEYED 1
159#define CONFIG_AUTOBOOT_PROMPT \
160 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
161#undef CONFIG_AUTOBOOT_DELAY_STR
162#define CONFIG_AUTOBOOT_STOP_STR " "
163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese53cf9432003-06-05 15:39:44 +0000165
wdenkc6097192002-11-03 00:24:07 +0000166/*-----------------------------------------------------------------------
167 * PCI stuff
168 *-----------------------------------------------------------------------
169 */
stroesea20b27a2004-12-16 18:05:42 +0000170#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
171#define PCI_HOST_FORCE 1 /* configure as pci host */
172#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000173
stroesea20b27a2004-12-16 18:05:42 +0000174#define CONFIG_PCI /* include pci support */
175#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
176#define CONFIG_PCI_PNP /* do pci plug-and-play */
177 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000178
stroesea20b27a2004-12-16 18:05:42 +0000179#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000180
stroesea20b27a2004-12-16 18:05:42 +0000181#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
stroesead10dd92003-02-14 11:21:23 +0000182
stroesea20b27a2004-12-16 18:05:42 +0000183#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
186#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
187#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
188#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
189#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
190#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
191#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
192#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
193#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
194#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000195
Matthias Fuchs82379b52009-09-07 17:00:41 +0200196#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
197
wdenkc6097192002-11-03 00:24:07 +0000198/*-----------------------------------------------------------------------
199 * IDE/ATA stuff
200 *-----------------------------------------------------------------------
201 */
wdenkc837dcb2004-01-20 23:12:12 +0000202#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
203#undef CONFIG_IDE_LED /* no led for ide supported */
wdenkc6097192002-11-03 00:24:07 +0000204#define CONFIG_IDE_RESET 1 /* reset for ide supported */
205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
207#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
210#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
213#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
214#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
wdenkc6097192002-11-03 00:24:07 +0000215
216/*-----------------------------------------------------------------------
217 * Start addresses for the final memory configuration
218 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000220 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_SDRAM_BASE 0x00000000
222#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
223#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
224#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
225#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000226
Matthias Fuchs3ba605d2009-01-02 12:18:49 +0100227#define CONFIG_PRAM 0 /* use pram variable to overwrite */
228
wdenkc6097192002-11-03 00:24:07 +0000229/*
230 * For booting Linux, the board info and command line data
231 * have to be in the first 8 MB of memory, since this is
232 * the maximum mapped by the Linux kernel during initialization.
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchsac53ee82008-09-05 15:34:04 +0200235
236#define CONFIG_OF_LIBFDT
237#define CONFIG_OF_BOARD_SETUP
238
wdenkc6097192002-11-03 00:24:07 +0000239/*-----------------------------------------------------------------------
240 * FLASH organization
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
243#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
246#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
249#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
250#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000251/*
252 * The following defines are added for buggy IOP480 byte interface.
253 * All other boards should use the standard values (CPCI405 etc.)
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
256#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
257#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000260
wdenkc6097192002-11-03 00:24:07 +0000261#if 0 /* Use NVRAM for environment variables */
262/*-----------------------------------------------------------------------
263 * NVRAM organization
264 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200265#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200266#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
267#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
wdenkc6097192002-11-03 00:24:07 +0000269
270#else /* Use EEPROM for environment variables */
271
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200272#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200273#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
274#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
wdenk8bde7f72003-06-27 21:31:46 +0000275 /* total size of a CAT24WC16 is 2048 bytes */
wdenkc6097192002-11-03 00:24:07 +0000276#endif
277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
279#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
280#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
wdenkc6097192002-11-03 00:24:07 +0000281
282/*-----------------------------------------------------------------------
283 * I2C EEPROM (CAT24WC16) for environment
284 */
285#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200286#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
288#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc6097192002-11-03 00:24:07 +0000289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
291#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000292/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
294#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenkc6097192002-11-03 00:24:07 +0000295 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000296 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000298
wdenkc6097192002-11-03 00:24:07 +0000299/*
300 * Init Memory Controller:
301 *
302 * BR0/1 and OR0/1 (FLASH)
303 */
304
305#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
306#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
307
308/*-----------------------------------------------------------------------
309 * External Bus Controller (EBC) Setup
310 */
311
wdenkc837dcb2004-01-20 23:12:12 +0000312/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_EBC_PB0AP 0x92015480
314#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000315
wdenkc837dcb2004-01-20 23:12:12 +0000316/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_EBC_PB1AP 0x92015480
318#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000319
wdenkc837dcb2004-01-20 23:12:12 +0000320/* Memory Bank 2 (CAN0, 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
322#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
323#define CONFIG_SYS_LED_ADDR 0xF0000380
wdenkc6097192002-11-03 00:24:07 +0000324
wdenkc837dcb2004-01-20 23:12:12 +0000325/* Memory Bank 3 (CompactFlash IDE) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
327#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000328
wdenkc837dcb2004-01-20 23:12:12 +0000329/* Memory Bank 4 (NVRAM/RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
331#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
332#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000333
wdenkc837dcb2004-01-20 23:12:12 +0000334/* Memory Bank 5 (optional Quart) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
336#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000337
wdenkc837dcb2004-01-20 23:12:12 +0000338/* Memory Bank 6 (FPGA internal) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
340#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
341#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
wdenkc6097192002-11-03 00:24:07 +0000342
343/*-----------------------------------------------------------------------
344 * FPGA stuff
345 */
346/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_FPGA_MODE 0x00
348#define CONFIG_SYS_FPGA_STATUS 0x02
349#define CONFIG_SYS_FPGA_TS 0x04
350#define CONFIG_SYS_FPGA_TS_LOW 0x06
351#define CONFIG_SYS_FPGA_TS_CAP0 0x10
352#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
353#define CONFIG_SYS_FPGA_TS_CAP1 0x14
354#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
355#define CONFIG_SYS_FPGA_TS_CAP2 0x18
356#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
357#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
358#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
wdenkc6097192002-11-03 00:24:07 +0000359
360/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
362#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
363#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
364#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
365#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
366#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
wdenkc6097192002-11-03 00:24:07 +0000367
368/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
370#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
371#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
372#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
373#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
wdenkc6097192002-11-03 00:24:07 +0000374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
376#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
wdenkc6097192002-11-03 00:24:07 +0000377
378/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
380#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
381#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
382#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
383#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
wdenkc6097192002-11-03 00:24:07 +0000384
385/*-----------------------------------------------------------------------
386 * Definitions for initial stack pointer and data area (in data cache)
387 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
wdenkc6097192002-11-03 00:24:07 +0000389
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
391#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
392#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
393#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
394#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000395
396
397/*
398 * Internal Definitions
399 *
400 * Boot Flags
401 */
402#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
403#define BOOTFLAG_WARM 0x02 /* Software reboot */
404
405#endif /* __CONFIG_H */