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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
Dave Liu03051c32007-09-18 12:36:11 +08002 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
Eran Libertyf046ccd2005-07-28 10:08:46 -050021 */
22
23/*
24 * CPU specific code for the MPC83xx family.
25 *
26 * Derived from the MPC8260 and MPC85xx.
27 */
28
29#include <common.h>
30#include <watchdog.h>
31#include <command.h>
32#include <mpc83xx.h>
33#include <asm/processor.h>
Gerald Van Baren213bf8c2007-03-31 12:23:51 -040034#include <libfdt.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050035
Wolfgang Denkd87080b2006-03-31 18:32:53 +020036DECLARE_GLOBAL_DATA_PTR;
37
Eran Libertyf046ccd2005-07-28 10:08:46 -050038int checkcpu(void)
39{
Dave Liu5f820432006-11-03 19:33:44 -060040 volatile immap_t *immr;
Eran Libertyf046ccd2005-07-28 10:08:46 -050041 ulong clock = gd->cpu_clk;
42 u32 pvr = get_pvr();
Dave Liu5f820432006-11-03 19:33:44 -060043 u32 spridr;
Eran Libertyf046ccd2005-07-28 10:08:46 -050044 char buf[32];
Kim Phillipse5c4ade2008-03-28 10:19:07 -050045 int i;
46
47#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
48 const struct cpu_type {
49 char name[15];
50 u32 partid;
51 } cpu_type_list [] = {
52 CPU_TYPE_ENTRY(8311),
53 CPU_TYPE_ENTRY(8313),
54 CPU_TYPE_ENTRY(8314),
55 CPU_TYPE_ENTRY(8315),
56 CPU_TYPE_ENTRY(8321),
57 CPU_TYPE_ENTRY(8323),
58 CPU_TYPE_ENTRY(8343),
59 CPU_TYPE_ENTRY(8347_TBGA_),
60 CPU_TYPE_ENTRY(8347_PBGA_),
61 CPU_TYPE_ENTRY(8349),
62 CPU_TYPE_ENTRY(8358_TBGA_),
63 CPU_TYPE_ENTRY(8358_PBGA_),
64 CPU_TYPE_ENTRY(8360),
65 CPU_TYPE_ENTRY(8377),
66 CPU_TYPE_ENTRY(8378),
67 CPU_TYPE_ENTRY(8379),
68 };
Eran Libertyf046ccd2005-07-28 10:08:46 -050069
Timur Tabid239d742006-11-03 12:00:28 -060070 immr = (immap_t *)CFG_IMMR;
Dave Liu5f820432006-11-03 19:33:44 -060071
Kim Phillips54b2d432007-04-30 15:26:21 -050072 puts("CPU: ");
Scott Wood95e7ef82007-04-16 14:34:16 -050073
74 switch (pvr & 0xffff0000) {
75 case PVR_E300C1:
76 printf("e300c1, ");
77 break;
78
79 case PVR_E300C2:
80 printf("e300c2, ");
81 break;
82
83 case PVR_E300C3:
84 printf("e300c3, ");
85 break;
86
Dave Liu03051c32007-09-18 12:36:11 +080087 case PVR_E300C4:
88 printf("e300c4, ");
89 break;
90
Scott Wood95e7ef82007-04-16 14:34:16 -050091 default:
92 printf("Unknown core, ");
Eran Libertyf046ccd2005-07-28 10:08:46 -050093 }
94
Dave Liu5f820432006-11-03 19:33:44 -060095 spridr = immr->sysconf.spridr;
Rafal Jaworowski6902df52005-10-17 02:39:53 +020096
Kim Phillipse5c4ade2008-03-28 10:19:07 -050097 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
98 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
99 puts("MPC");
100 puts(cpu_type_list[i].name);
101 if (IS_E_PROCESSOR(spridr))
102 puts("E");
103 if (REVID_MAJOR(spridr) >= 2)
104 puts("A");
105 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
106 REVID_MINOR(spridr));
107 break;
108 }
109
110 if (i == ARRAY_SIZE(cpu_type_list))
111 printf("(SPRIDR %08x unknown), ", spridr);
112
113 printf(" at %s MHz, ", strmhz(buf, clock));
114
115 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
Kim Phillips54b2d432007-04-30 15:26:21 -0500116
Eran Libertyf046ccd2005-07-28 10:08:46 -0500117 return 0;
118}
119
120
Timur Tabibe5e6182006-11-03 19:15:00 -0600121/*
Timur Tabi2ad6b512006-10-31 18:44:42 -0600122 * Program a UPM with the code supplied in the table.
123 *
124 * The 'dummy' variable is used to increment the MAD. 'dummy' is
125 * supposed to be a pointer to the memory of the device being
126 * programmed by the UPM. The data in the MDR is written into
127 * memory and the MAD is incremented every time there's a read
128 * from 'dummy'. Unfortunately, the current prototype for this
129 * function doesn't allow for passing the address of this
130 * device, and changing the prototype will break a number lots
131 * of other code, so we need to use a round-about way of finding
132 * the value for 'dummy'.
133 *
134 * The value can be extracted from the base address bits of the
135 * Base Register (BR) associated with the specific UPM. To find
136 * that BR, we need to scan all 8 BRs until we find the one that
137 * has its MSEL bits matching the UPM we want. Once we know the
138 * right BR, we can extract the base address bits from it.
139 *
140 * The MxMR and the BR and OR of the chosen bank should all be
141 * configured before calling this function.
142 *
143 * Parameters:
144 * upm: 0=UPMA, 1=UPMB, 2=UPMC
145 * table: Pointer to an array of values to program
146 * size: Number of elements in the array. Must be 64 or less.
Timur Tabibe5e6182006-11-03 19:15:00 -0600147 */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500148void upmconfig (uint upm, uint *table, uint size)
149{
Timur Tabi2ad6b512006-10-31 18:44:42 -0600150#if defined(CONFIG_MPC834X)
Timur Tabid239d742006-11-03 12:00:28 -0600151 volatile immap_t *immap = (immap_t *) CFG_IMMR;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600152 volatile lbus83xx_t *lbus = &immap->lbus;
153 volatile uchar *dummy = NULL;
154 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
155 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
156 uint i;
157
158 /* Scan all the banks to determine the base address of the device */
159 for (i = 0; i < 8; i++) {
160 if ((lbus->bank[i].br & BR_MSEL) == msel) {
161 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
162 break;
163 }
164 }
165
166 if (!dummy) {
167 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
168 hang();
169 }
170
171 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
172 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
173
174 for (i = 0; i < size; i++) {
175 lbus->mdr = table[i];
176 __asm__ __volatile__ ("sync");
177 *dummy; /* Write the value to memory and increment MAD */
178 __asm__ __volatile__ ("sync");
179 }
180
181 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
182 *mxmr &= 0xCFFFFFC0;
183#else
184 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
185 hang();
186#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500187}
188
189
190int
191do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
192{
Wolfgang Denk07a25052005-08-05 19:49:35 +0200193 ulong msr;
194#ifndef MPC83xx_RESET
195 ulong addr;
196#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500197
Timur Tabid239d742006-11-03 12:00:28 -0600198 volatile immap_t *immap = (immap_t *) CFG_IMMR;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500199
200#ifdef MPC83xx_RESET
201 /* Interrupts and MMU off */
202 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
203
204 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
205 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
206
207 /* enable Reset Control Reg */
208 immap->reset.rpr = 0x52535445;
Marian Balakowicz6d8ae5a2006-03-14 16:12:48 +0100209 __asm__ __volatile__ ("sync");
210 __asm__ __volatile__ ("isync");
Eran Libertyf046ccd2005-07-28 10:08:46 -0500211
212 /* confirm Reset Control Reg is enabled */
213 while(!((immap->reset.rcer) & RCER_CRE));
214
215 printf("Resetting the board.");
216 printf("\n");
217
218 udelay(200);
219
220 /* perform reset, only one bit */
Wolfgang Denk07a25052005-08-05 19:49:35 +0200221 immap->reset.rcr = RCR_SWHR;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500222
Wolfgang Denk07a25052005-08-05 19:49:35 +0200223#else /* ! MPC83xx_RESET */
224
225 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
226
227 /* Interrupts and MMU off */
228 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500229
230 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
231 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
232
233 /*
234 * Trying to execute the next instruction at a non-existing address
235 * should cause a machine check, resulting in reset
236 */
237 addr = CFG_RESET_ADDRESS;
238
239 printf("resetting the board.");
240 printf("\n");
241 ((void (*)(void)) addr) ();
Wolfgang Denk07a25052005-08-05 19:49:35 +0200242#endif /* MPC83xx_RESET */
243
Eran Libertyf046ccd2005-07-28 10:08:46 -0500244 return 1;
245}
246
247
248/*
249 * Get timebase clock frequency (like cpu_clk in Hz)
250 */
251
252unsigned long get_tbclk(void)
253{
Eran Libertyf046ccd2005-07-28 10:08:46 -0500254 ulong tbclk;
255
256 tbclk = (gd->bus_clk + 3L) / 4L;
257
258 return tbclk;
259}
260
261
262#if defined(CONFIG_WATCHDOG)
263void watchdog_reset (void)
264{
Timur Tabi2ad6b512006-10-31 18:44:42 -0600265 int re_enable = disable_interrupts();
266
267 /* Reset the 83xx watchdog */
Timur Tabid239d742006-11-03 12:00:28 -0600268 volatile immap_t *immr = (immap_t *) CFG_IMMR;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600269 immr->wdt.swsrr = 0x556c;
270 immr->wdt.swsrr = 0xaa39;
271
272 if (re_enable)
273 enable_interrupts ();
Eran Libertyf046ccd2005-07-28 10:08:46 -0500274}
Timur Tabi2ad6b512006-10-31 18:44:42 -0600275#endif
Kumar Gala62ec6412006-01-11 16:48:10 -0600276
Marian Balakowicz61f25152006-03-14 16:14:48 +0100277#if defined(CONFIG_DDR_ECC)
278void dma_init(void)
279{
Timur Tabid239d742006-11-03 12:00:28 -0600280 volatile immap_t *immap = (immap_t *)CFG_IMMR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500281 volatile dma83xx_t *dma = &immap->dma;
Marian Balakowicz61f25152006-03-14 16:14:48 +0100282 volatile u32 status = swab32(dma->dmasr0);
283 volatile u32 dmamr0 = swab32(dma->dmamr0);
284
285 debug("DMA-init\n");
286
287 /* initialize DMASARn, DMADAR and DMAABCRn */
288 dma->dmadar0 = (u32)0;
289 dma->dmasar0 = (u32)0;
290 dma->dmabcr0 = 0;
291
292 __asm__ __volatile__ ("sync");
293 __asm__ __volatile__ ("isync");
294
295 /* clear CS bit */
296 dmamr0 &= ~DMA_CHANNEL_START;
297 dma->dmamr0 = swab32(dmamr0);
298 __asm__ __volatile__ ("sync");
299 __asm__ __volatile__ ("isync");
300
301 /* while the channel is busy, spin */
302 while(status & DMA_CHANNEL_BUSY) {
303 status = swab32(dma->dmasr0);
304 }
305
306 debug("DMA-init end\n");
307}
308
309uint dma_check(void)
310{
Timur Tabid239d742006-11-03 12:00:28 -0600311 volatile immap_t *immap = (immap_t *)CFG_IMMR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500312 volatile dma83xx_t *dma = &immap->dma;
Marian Balakowicz61f25152006-03-14 16:14:48 +0100313 volatile u32 status = swab32(dma->dmasr0);
314 volatile u32 byte_count = swab32(dma->dmabcr0);
315
316 /* while the channel is busy, spin */
317 while (status & DMA_CHANNEL_BUSY) {
318 status = swab32(dma->dmasr0);
319 }
320
321 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
322 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
323 }
324
325 return status;
326}
327
328int dma_xfer(void *dest, u32 count, void *src)
329{
Timur Tabid239d742006-11-03 12:00:28 -0600330 volatile immap_t *immap = (immap_t *)CFG_IMMR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500331 volatile dma83xx_t *dma = &immap->dma;
Marian Balakowicz61f25152006-03-14 16:14:48 +0100332 volatile u32 dmamr0;
333
334 /* initialize DMASARn, DMADAR and DMAABCRn */
335 dma->dmadar0 = swab32((u32)dest);
336 dma->dmasar0 = swab32((u32)src);
337 dma->dmabcr0 = swab32(count);
338
339 __asm__ __volatile__ ("sync");
340 __asm__ __volatile__ ("isync");
341
342 /* init direct transfer, clear CS bit */
343 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
344 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
345 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200346
Marian Balakowicz61f25152006-03-14 16:14:48 +0100347 dma->dmamr0 = swab32(dmamr0);
348
349 __asm__ __volatile__ ("sync");
350 __asm__ __volatile__ ("isync");
351
352 /* set CS to start DMA transfer */
353 dmamr0 |= DMA_CHANNEL_START;
354 dma->dmamr0 = swab32(dmamr0);
355 __asm__ __volatile__ ("sync");
356 __asm__ __volatile__ ("isync");
357
358 return ((int)dma_check());
359}
360#endif /*CONFIG_DDR_ECC*/