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Aneesh V16dc7022011-09-08 11:05:49 -04001/*
2 * (C) Copyright 2010
3 * Texas Instruments Incorporated.
4 * Aneesh V <aneesh@ti.com>
5 * Steve Sakoman <steve@sakoman.com>
6 *
7 * TI OMAP4 common configuration settings
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_OMAP4_COMMON_H
29#define __CONFIG_OMAP4_COMMON_H
30
31/*
32 * High Level Configuration Options
33 */
34#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
35#define CONFIG_OMAP 1 /* in a TI OMAP core */
36#define CONFIG_OMAP44XX 1 /* which is a 44XX */
37#define CONFIG_OMAP4430 1 /* which is in a 4430 */
38#define CONFIG_ARCH_CPU_INIT
39
40/* Get CPU defs */
41#include <asm/arch/cpu.h>
Sricharan508a58f2011-11-15 09:49:55 -050042#include <asm/arch/omap.h>
Aneesh V16dc7022011-09-08 11:05:49 -040043
44/* Display CPU and Board Info */
45#define CONFIG_DISPLAY_CPUINFO 1
46#define CONFIG_DISPLAY_BOARDINFO 1
47
48/* Clock Defines */
49#define V_OSCK 38400000 /* Clock output from T2 */
50#define V_SCLK V_OSCK
51
52#undef CONFIG_USE_IRQ /* no support for IRQs */
53#define CONFIG_MISC_INIT_R
54
55#define CONFIG_OF_LIBFDT 1
56
57#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
58#define CONFIG_SETUP_MEMORY_TAGS 1
59#define CONFIG_INITRD_TAG 1
60#define CONFIG_REVISION_TAG 1
61
62/*
63 * Size of malloc() pool
64 * Total Size Environment - 128k
65 * Malloc - add 256k
66 */
67#define CONFIG_ENV_SIZE (128 << 10)
68#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
69/* Vector Base */
70#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
71
72/*
73 * Hardware drivers
74 */
75
76/*
77 * serial port - NS16550 compatible
78 */
79#define V_NS16550_CLK 48000000
80
81#define CONFIG_SYS_NS16550
82#define CONFIG_SYS_NS16550_SERIAL
83#define CONFIG_SYS_NS16550_REG_SIZE (-4)
84#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
85#define CONFIG_CONS_INDEX 3
86#define CONFIG_SYS_NS16550_COM3 UART3_BASE
87
88#define CONFIG_BAUDRATE 115200
89#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
90 115200}
91/* I2C */
92#define CONFIG_HARD_I2C 1
93#define CONFIG_SYS_I2C_SPEED 100000
94#define CONFIG_SYS_I2C_SLAVE 1
95#define CONFIG_SYS_I2C_BUS 0
96#define CONFIG_SYS_I2C_BUS_SELECT 1
97#define CONFIG_DRIVER_OMAP34XX_I2C 1
98#define CONFIG_I2C_MULTI_BUS 1
99
100/* TWL6030 */
Balaji T K14fa2dd2011-09-08 06:34:57 +0000101#ifndef CONFIG_SPL_BUILD
Aneesh V16dc7022011-09-08 11:05:49 -0400102#define CONFIG_TWL6030_POWER 1
Balaji T K14fa2dd2011-09-08 06:34:57 +0000103#endif
Aneesh V16dc7022011-09-08 11:05:49 -0400104
105/* MMC */
106#define CONFIG_GENERIC_MMC 1
107#define CONFIG_MMC 1
108#define CONFIG_OMAP_HSMMC 1
109#define CONFIG_SYS_MMC_SET_DEV 1
110#define CONFIG_DOS_PARTITION 1
111
112
113/* USB */
114#define CONFIG_MUSB_UDC 1
115#define CONFIG_USB_OMAP3 1
116
117/* USB device configuration */
118#define CONFIG_USB_DEVICE 1
119#define CONFIG_USB_TTY 1
120#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
121
122/* Flash */
123#define CONFIG_SYS_NO_FLASH 1
124
Sricharan78f455c2011-11-15 09:50:03 -0500125/* clocks */
126#define CONFIG_SYS_CLOCKS_ENABLE_ALL
127
Aneesh V16dc7022011-09-08 11:05:49 -0400128/* commands to include */
129#include <config_cmd_default.h>
130
131/* Enabled commands */
132#define CONFIG_CMD_EXT2 /* EXT2 Support */
133#define CONFIG_CMD_FAT /* FAT support */
134#define CONFIG_CMD_I2C /* I2C serial bus support */
135#define CONFIG_CMD_MMC /* MMC support */
136
137/* Disabled commands */
138#undef CONFIG_CMD_NET
139#undef CONFIG_CMD_NFS
140#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
141#undef CONFIG_CMD_IMLS /* List all found images */
142
143/*
144 * Environment setup
145 */
146
147#define CONFIG_BOOTDELAY 3
148
149#define CONFIG_ENV_OVERWRITE
150
151#define CONFIG_EXTRA_ENV_SETTINGS \
152 "loadaddr=0x82000000\0" \
Aneesh Vd71a4912011-11-21 23:38:58 +0000153 "console=ttyO2,115200n8\0" \
Aneesh V16dc7022011-09-08 11:05:49 -0400154 "usbtty=cdc_acm\0" \
155 "vram=16M\0" \
156 "mmcdev=0\0" \
157 "mmcroot=/dev/mmcblk0p2 rw\0" \
158 "mmcrootfstype=ext3 rootwait\0" \
159 "mmcargs=setenv bootargs console=${console} " \
160 "vram=${vram} " \
161 "root=${mmcroot} " \
162 "rootfstype=${mmcrootfstype}\0" \
163 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
164 "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
165 "source ${loadaddr}\0" \
166 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
167 "mmcboot=echo Booting from mmc${mmcdev} ...; " \
168 "run mmcargs; " \
169 "bootm ${loadaddr}\0" \
170
171#define CONFIG_BOOTCOMMAND \
172 "if mmc rescan ${mmcdev}; then " \
173 "if run loadbootscript; then " \
174 "run bootscript; " \
175 "else " \
176 "if run loaduimage; then " \
177 "run mmcboot; " \
178 "fi; " \
179 "fi; " \
180 "fi"
181
182#define CONFIG_AUTO_COMPLETE 1
183
184/*
185 * Miscellaneous configurable options
186 */
187
188#define CONFIG_SYS_LONGHELP /* undef to save memory */
189#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
190#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
191#define CONFIG_SYS_CBSIZE 512
192/* Print Buffer Size */
193#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
194 sizeof(CONFIG_SYS_PROMPT) + 16)
195#define CONFIG_SYS_MAXARGS 16
196/* Boot Argument Buffer Size */
197#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
198
199/*
200 * memtest setup
201 */
202#define CONFIG_SYS_MEMTEST_START 0x80000000
203#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
204
205/* Default load address */
206#define CONFIG_SYS_LOAD_ADDR 0x80000000
207
208/* Use General purpose timer 1 */
209#define CONFIG_SYS_TIMERBASE GPT2_BASE
210#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
211#define CONFIG_SYS_HZ 1000
212
213/*
214 * Stack sizes
215 *
216 * The stack sizes are set up in start.S using the settings below
217 */
218#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
219#ifdef CONFIG_USE_IRQ
220#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
221#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
222#endif
223
224/*
225 * SDRAM Memory Map
226 * Even though we use two CS all the memory
227 * is mapped to one contiguous block
228 */
229#define CONFIG_NR_DRAM_BANKS 1
230
231#define CONFIG_SYS_SDRAM_BASE 0x80000000
232#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
233#define CONFIG_SYS_INIT_RAM_SIZE 0x800
234#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
235 CONFIG_SYS_INIT_RAM_SIZE - \
236 GENERATED_GBL_DATA_SIZE)
237
238#ifndef CONFIG_SYS_L2CACHE_OFF
239#define CONFIG_SYS_L2_PL310 1
240#define CONFIG_SYS_PL310_BASE 0x48242000
241#endif
Aneesh V8e408522011-11-21 23:38:59 +0000242#define CONFIG_SYS_CACHELINE_SIZE 32
Aneesh V16dc7022011-09-08 11:05:49 -0400243
244/* Defines for SDRAM init */
SRICHARAN R8e706912011-09-27 01:43:18 +0000245#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
246
Aneesh V16dc7022011-09-08 11:05:49 -0400247#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
248#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
249#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
250#endif
251
252/* Defines for SPL */
253#define CONFIG_SPL
254#define CONFIG_SPL_TEXT_BASE 0x40304350
255#define CONFIG_SPL_MAX_SIZE (38 * 1024)
256#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
257
Aneesh V2d01dd92011-10-21 12:29:34 -0400258/*
Aneesh V2d01dd92011-10-21 12:29:34 -0400259 * 64 bytes before this address should be set aside for u-boot.img's
Aneesh Vf6ddfdd2011-11-21 23:39:04 +0000260 * header. That is 80E7FFC0--0x80E80000 should not be used for any
Aneesh V2d01dd92011-10-21 12:29:34 -0400261 * other needs.
262 */
Aneesh Vf6ddfdd2011-11-21 23:39:04 +0000263#define CONFIG_SYS_TEXT_BASE 0x80E80000
Aneesh V2d01dd92011-10-21 12:29:34 -0400264
Aneesh Vf6ddfdd2011-11-21 23:39:04 +0000265/*
266 * BSS and malloc area 64MB into memory to allow enough
267 * space for the kernel at the beginning of memory
268 */
269#define CONFIG_SPL_BSS_START_ADDR 0x84000000
270#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
271#define CONFIG_SYS_SPL_MALLOC_START 0x84100000
272#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
Aneesh V16dc7022011-09-08 11:05:49 -0400273
274#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
275#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
276#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
277#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
278
279#define CONFIG_SPL_LIBCOMMON_SUPPORT
280#define CONFIG_SPL_LIBDISK_SUPPORT
281#define CONFIG_SPL_I2C_SUPPORT
282#define CONFIG_SPL_MMC_SUPPORT
283#define CONFIG_SPL_FAT_SUPPORT
284#define CONFIG_SPL_LIBGENERIC_SUPPORT
285#define CONFIG_SPL_SERIAL_SUPPORT
286#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
287
Sricharan78f455c2011-11-15 09:50:03 -0500288#define CONFIG_SYS_ENABLE_PADS_ALL
289
Aneesh V16dc7022011-09-08 11:05:49 -0400290#endif /* __CONFIG_OMAP4_COMMON_H */