blob: 97006116f4ed6ee2479a28b2a0b4da3a5f519be0 [file] [log] [blame]
Stefan Roesee53b5072009-06-09 11:50:40 +02001/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009 Dave Srl www.dave.eu
4 * (C) Copyright 2009 Stefan Roese <sr@denx.de>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesee53b5072009-06-09 11:50:40 +02007 */
8
9#include <common.h>
10#include <asm/bitops.h>
11#include <command.h>
12#include <asm/io.h>
13#include <asm/processor.h>
Wolfgang Denk7629f1c2009-06-14 20:58:47 +020014#include <asm/mpc512x.h>
Stefan Roesee53b5072009-06-09 11:50:40 +020015#include <fdt_support.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
Stefan Roesee53b5072009-06-09 11:50:40 +020019int eeprom_write_enable(unsigned dev_addr, int state)
20{
21 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
22
23 if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
24 return -1;
25
26 if (state == 0)
27 setbits_be32(&im->gpio.gpdat, 0x00100000);
28 else
29 clrbits_be32(&im->gpio.gpdat, 0x00100000);
30
Wolfgang Denk7629f1c2009-06-14 20:58:47 +020031 return 0;
Stefan Roesee53b5072009-06-09 11:50:40 +020032}
33
34int board_early_init_f(void)
35{
36 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
Wolfgang Denk05493532009-06-14 20:58:46 +020037 int i;
Stefan Roesee53b5072009-06-09 11:50:40 +020038
39 /*
Stefan Roesee53b5072009-06-09 11:50:40 +020040 * Initialize Local Window for boot access
41 */
42 out_be32(&im->sysconf.lpbaw,
43 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
44 sync_law(&im->sysconf.lpbaw);
45
46 /*
Stefan Roesee53b5072009-06-09 11:50:40 +020047 * Configure MSCAN clocks
48 */
Wolfgang Denk05493532009-06-14 20:58:46 +020049 for (i=0; i<4; ++i) {
50 out_be32(&im->clk.msccr[i], 0x00300000);
51 out_be32(&im->clk.msccr[i], 0x00310000);
52 }
Stefan Roesee53b5072009-06-09 11:50:40 +020053
54 /*
55 * Configure GPIO's
56 */
57 clrbits_be32(&im->gpio.gpodr, 0x000000e0);
58 clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
59 setbits_be32(&im->gpio.gpdir, 0x001000e0);
60 setbits_be32(&im->gpio.gpdat, 0x00100000);
61
62 return 0;
63}
64
Stefan Roesee53b5072009-06-09 11:50:40 +020065phys_size_t initdram(int board_type)
66{
Martha M Stan054197b2009-09-21 14:07:14 -040067 return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
Stefan Roesee53b5072009-06-09 11:50:40 +020068}
69
70int misc_init_r(void)
71{
72 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
73 u32 val;
74
75 /*
76 * Optimize access to profibus chip (VPC3) on the local bus
77 */
78
79 /*
80 * Select 1:1 for LPC_DIV
81 */
82 val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
83 out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
84
85 /*
86 * Configure LPC Chips Select Deadcycle Control Register
87 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
88 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
89 */
90 clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
91 setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
92
93 /*
94 * Configure LPC Chips Select Holdcycle Control Register
95 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
96 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
97 */
98 clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
99 setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
100
101 return 0;
102}
103
104static iopin_t ioregs_init[] = {
105 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
106 {
107 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
108 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
109 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
110 },
111 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
112 {
113 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
114 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
115 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
116 },
117 /* FUNC1=SELECT LPC_CS1 */
118 {
119 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
120 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
121 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
122 },
123 /* FUNC3=SELECT PSC5_2 */
124 {
125 offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
126 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
127 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
128 },
129 /* FUNC3=SELECT PSC5_3 */
130 {
131 offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
132 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
133 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
134 },
135 /* FUNC3=SELECT PSC7_3 */
136 {
137 offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
138 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
139 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
140 },
141 /* FUNC3=SELECT PSC9_0 */
142 {
143 offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
144 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
145 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
146 },
147 /* FUNC3=SELECT PSC10_0 */
148 {
149 offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
150 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
151 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
152 },
153 /* FUNC3=SELECT PSC10_3 */
154 {
155 offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
156 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
157 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
158 },
159 /* FUNC3=SELECT PSC11_0 */
160 {
161 offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
162 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
163 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
164 },
165 /* FUNC0=SELECT IRQ0 */
166 {
167 offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
168 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
169 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
170 }
171};
172
173static iopin_t rev2_silicon_pci_ioregs_init[] = {
174 /* FUNC0=PCI Sets next 54 to PCI pads */
175 {
176 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
177 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
178 }
179};
180
181int checkboard(void)
182{
183 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
184 u32 spridr;
185
186 puts("Board: MECP_5123\n");
187
188 /*
189 * Initialize function mux & slew rate IO inter alia on IO
190 * Pins
191 */
192 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
193
194 spridr = in_be32(&im->sysconf.spridr);
195 if (SVR_MJREV(spridr) >= 2)
196 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
197
198 return 0;
199}
200
201#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
202void ft_board_setup(void *blob, bd_t *bd)
203{
204 ft_cpu_setup(blob, bd);
Stefan Roesee53b5072009-06-09 11:50:40 +0200205}
206#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */