blob: 4482dc621d692f30445f28d56ff793ecbd844767 [file] [log] [blame]
Oleksandr Tymoshenko6e9e0622014-02-01 21:51:25 -07001/*
2 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __DWC2_H__
8#define __DWC2_H__
9
10struct dwc2_hc_regs {
11 u32 hcchar; /* 0x00 */
12 u32 hcsplt;
13 u32 hcint;
14 u32 hcintmsk;
15 u32 hctsiz; /* 0x10 */
16 u32 hcdma;
17 u32 reserved;
18 u32 hcdmab;
19};
20
21struct dwc2_host_regs {
22 u32 hcfg; /* 0x00 */
23 u32 hfir;
24 u32 hfnum;
25 u32 _pad_0x40c;
26 u32 hptxsts; /* 0x10 */
27 u32 haint;
28 u32 haintmsk;
29 u32 hflbaddr;
30};
31
32struct dwc2_core_regs {
33 u32 gotgctl; /* 0x000 */
34 u32 gotgint;
35 u32 gahbcfg;
36 u32 gusbcfg;
37 u32 grstctl; /* 0x010 */
38 u32 gintsts;
39 u32 gintmsk;
40 u32 grxstsr;
41 u32 grxstsp; /* 0x020 */
42 u32 grxfsiz;
43 u32 gnptxfsiz;
44 u32 gnptxsts;
45 u32 gi2cctl; /* 0x030 */
46 u32 gpvndctl;
47 u32 ggpio;
48 u32 guid;
49 u32 gsnpsid; /* 0x040 */
50 u32 ghwcfg1;
51 u32 ghwcfg2;
52 u32 ghwcfg3;
53 u32 ghwcfg4; /* 0x050 */
54 u32 glpmcfg;
55 u32 _pad_0x58_0x9c[42];
56 u32 hptxfsiz; /* 0x100 */
57 u32 dptxfsiz_dieptxf[15];
58 u32 _pad_0x140_0x3fc[176];
59 struct dwc2_host_regs host_regs; /* 0x400 */
60 u32 _pad_0x420_0x43c[8];
61 u32 hprt0; /* 0x440 */
62 u32 _pad_0x444_0x4fc[47];
63 struct dwc2_hc_regs hc_regs[16]; /* 0x500 */
64 u32 _pad_0x700_0xe00[448];
65 u32 pcgcctl; /* 0xe00 */
66};
67
68#define DWC2_GOTGCTL_SESREQSCS (1 << 0)
69#define DWC2_GOTGCTL_SESREQSCS_OFFSET 0
70#define DWC2_GOTGCTL_SESREQ (1 << 1)
71#define DWC2_GOTGCTL_SESREQ_OFFSET 1
72#define DWC2_GOTGCTL_HSTNEGSCS (1 << 8)
73#define DWC2_GOTGCTL_HSTNEGSCS_OFFSET 8
74#define DWC2_GOTGCTL_HNPREQ (1 << 9)
75#define DWC2_GOTGCTL_HNPREQ_OFFSET 9
76#define DWC2_GOTGCTL_HSTSETHNPEN (1 << 10)
77#define DWC2_GOTGCTL_HSTSETHNPEN_OFFSET 10
78#define DWC2_GOTGCTL_DEVHNPEN (1 << 11)
79#define DWC2_GOTGCTL_DEVHNPEN_OFFSET 11
80#define DWC2_GOTGCTL_CONIDSTS (1 << 16)
81#define DWC2_GOTGCTL_CONIDSTS_OFFSET 16
82#define DWC2_GOTGCTL_DBNCTIME (1 << 17)
83#define DWC2_GOTGCTL_DBNCTIME_OFFSET 17
84#define DWC2_GOTGCTL_ASESVLD (1 << 18)
85#define DWC2_GOTGCTL_ASESVLD_OFFSET 18
86#define DWC2_GOTGCTL_BSESVLD (1 << 19)
87#define DWC2_GOTGCTL_BSESVLD_OFFSET 19
88#define DWC2_GOTGCTL_OTGVER (1 << 20)
89#define DWC2_GOTGCTL_OTGVER_OFFSET 20
90#define DWC2_GOTGINT_SESENDDET (1 << 2)
91#define DWC2_GOTGINT_SESENDDET_OFFSET 2
92#define DWC2_GOTGINT_SESREQSUCSTSCHNG (1 << 8)
93#define DWC2_GOTGINT_SESREQSUCSTSCHNG_OFFSET 8
94#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG (1 << 9)
95#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 9
96#define DWC2_GOTGINT_RESERVER10_16_MASK (0x7F << 10)
97#define DWC2_GOTGINT_RESERVER10_16_OFFSET 10
98#define DWC2_GOTGINT_HSTNEGDET (1 << 17)
99#define DWC2_GOTGINT_HSTNEGDET_OFFSET 17
100#define DWC2_GOTGINT_ADEVTOUTCHNG (1 << 18)
101#define DWC2_GOTGINT_ADEVTOUTCHNG_OFFSET 18
102#define DWC2_GOTGINT_DEBDONE (1 << 19)
103#define DWC2_GOTGINT_DEBDONE_OFFSET 19
104#define DWC2_GAHBCFG_GLBLINTRMSK (1 << 0)
105#define DWC2_GAHBCFG_GLBLINTRMSK_OFFSET 0
106#define DWC2_GAHBCFG_HBURSTLEN_SINGLE (0 << 1)
107#define DWC2_GAHBCFG_HBURSTLEN_INCR (1 << 1)
108#define DWC2_GAHBCFG_HBURSTLEN_INCR4 (3 << 1)
109#define DWC2_GAHBCFG_HBURSTLEN_INCR8 (5 << 1)
110#define DWC2_GAHBCFG_HBURSTLEN_INCR16 (7 << 1)
111#define DWC2_GAHBCFG_HBURSTLEN_MASK (0xF << 1)
112#define DWC2_GAHBCFG_HBURSTLEN_OFFSET 1
113#define DWC2_GAHBCFG_DMAENABLE (1 << 5)
114#define DWC2_GAHBCFG_DMAENABLE_OFFSET 5
115#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL (1 << 7)
116#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL_OFFSET 7
117#define DWC2_GAHBCFG_PTXFEMPLVL (1 << 8)
118#define DWC2_GAHBCFG_PTXFEMPLVL_OFFSET 8
119#define DWC2_GUSBCFG_TOUTCAL_MASK (0x7 << 0)
120#define DWC2_GUSBCFG_TOUTCAL_OFFSET 0
121#define DWC2_GUSBCFG_PHYIF (1 << 3)
122#define DWC2_GUSBCFG_PHYIF_OFFSET 3
123#define DWC2_GUSBCFG_ULPI_UTMI_SEL (1 << 4)
124#define DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET 4
125#define DWC2_GUSBCFG_FSINTF (1 << 5)
126#define DWC2_GUSBCFG_FSINTF_OFFSET 5
127#define DWC2_GUSBCFG_PHYSEL (1 << 6)
128#define DWC2_GUSBCFG_PHYSEL_OFFSET 6
129#define DWC2_GUSBCFG_DDRSEL (1 << 7)
130#define DWC2_GUSBCFG_DDRSEL_OFFSET 7
131#define DWC2_GUSBCFG_SRPCAP (1 << 8)
132#define DWC2_GUSBCFG_SRPCAP_OFFSET 8
133#define DWC2_GUSBCFG_HNPCAP (1 << 9)
134#define DWC2_GUSBCFG_HNPCAP_OFFSET 9
135#define DWC2_GUSBCFG_USBTRDTIM_MASK (0xF << 10)
136#define DWC2_GUSBCFG_USBTRDTIM_OFFSET 10
137#define DWC2_GUSBCFG_NPTXFRWNDEN (1 << 14)
138#define DWC2_GUSBCFG_NPTXFRWNDEN_OFFSET 14
139#define DWC2_GUSBCFG_PHYLPWRCLKSEL (1 << 15)
140#define DWC2_GUSBCFG_PHYLPWRCLKSEL_OFFSET 15
141#define DWC2_GUSBCFG_OTGUTMIFSSEL (1 << 16)
142#define DWC2_GUSBCFG_OTGUTMIFSSEL_OFFSET 16
143#define DWC2_GUSBCFG_ULPI_FSLS (1 << 17)
144#define DWC2_GUSBCFG_ULPI_FSLS_OFFSET 17
145#define DWC2_GUSBCFG_ULPI_AUTO_RES (1 << 18)
146#define DWC2_GUSBCFG_ULPI_AUTO_RES_OFFSET 18
147#define DWC2_GUSBCFG_ULPI_CLK_SUS_M (1 << 19)
148#define DWC2_GUSBCFG_ULPI_CLK_SUS_M_OFFSET 19
149#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20)
150#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV_OFFSET 20
151#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR (1 << 21)
152#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET 21
153#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE (1 << 22)
154#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET 22
Dinh Nguyenb5ab6632016-03-04 18:57:04 -0600155#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH (1 << 24)
156#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH_OFFSET 24
Oleksandr Tymoshenko6e9e0622014-02-01 21:51:25 -0700157#define DWC2_GUSBCFG_IC_USB_CAP (1 << 26)
158#define DWC2_GUSBCFG_IC_USB_CAP_OFFSET 26
159#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE (1 << 27)
160#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE_OFFSET 27
161#define DWC2_GUSBCFG_TX_END_DELAY (1 << 28)
162#define DWC2_GUSBCFG_TX_END_DELAY_OFFSET 28
163#define DWC2_GUSBCFG_FORCEHOSTMODE (1 << 29)
164#define DWC2_GUSBCFG_FORCEHOSTMODE_OFFSET 29
165#define DWC2_GUSBCFG_FORCEDEVMODE (1 << 30)
166#define DWC2_GUSBCFG_FORCEDEVMODE_OFFSET 30
167#define DWC2_GLPMCTL_LPM_CAP_EN (1 << 0)
168#define DWC2_GLPMCTL_LPM_CAP_EN_OFFSET 0
169#define DWC2_GLPMCTL_APPL_RESP (1 << 1)
170#define DWC2_GLPMCTL_APPL_RESP_OFFSET 1
171#define DWC2_GLPMCTL_HIRD_MASK (0xF << 2)
172#define DWC2_GLPMCTL_HIRD_OFFSET 2
173#define DWC2_GLPMCTL_REM_WKUP_EN (1 << 6)
174#define DWC2_GLPMCTL_REM_WKUP_EN_OFFSET 6
175#define DWC2_GLPMCTL_EN_UTMI_SLEEP (1 << 7)
176#define DWC2_GLPMCTL_EN_UTMI_SLEEP_OFFSET 7
177#define DWC2_GLPMCTL_HIRD_THRES_MASK (0x1F << 8)
178#define DWC2_GLPMCTL_HIRD_THRES_OFFSET 8
179#define DWC2_GLPMCTL_LPM_RESP_MASK (0x3 << 13)
180#define DWC2_GLPMCTL_LPM_RESP_OFFSET 13
181#define DWC2_GLPMCTL_PRT_SLEEP_STS (1 << 15)
182#define DWC2_GLPMCTL_PRT_SLEEP_STS_OFFSET 15
183#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK (1 << 16)
184#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK_OFFSET 16
185#define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK (0xF << 17)
186#define DWC2_GLPMCTL_LPM_CHAN_INDEX_OFFSET 17
187#define DWC2_GLPMCTL_RETRY_COUNT_MASK (0x7 << 21)
188#define DWC2_GLPMCTL_RETRY_COUNT_OFFSET 21
189#define DWC2_GLPMCTL_SEND_LPM (1 << 24)
190#define DWC2_GLPMCTL_SEND_LPM_OFFSET 24
191#define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK (0x7 << 25)
192#define DWC2_GLPMCTL_RETRY_COUNT_STS_OFFSET 25
193#define DWC2_GLPMCTL_HSIC_CONNECT (1 << 30)
194#define DWC2_GLPMCTL_HSIC_CONNECT_OFFSET 30
195#define DWC2_GLPMCTL_INV_SEL_HSIC (1 << 31)
196#define DWC2_GLPMCTL_INV_SEL_HSIC_OFFSET 31
197#define DWC2_GRSTCTL_CSFTRST (1 << 0)
198#define DWC2_GRSTCTL_CSFTRST_OFFSET 0
199#define DWC2_GRSTCTL_HSFTRST (1 << 1)
200#define DWC2_GRSTCTL_HSFTRST_OFFSET 1
201#define DWC2_GRSTCTL_HSTFRM (1 << 2)
202#define DWC2_GRSTCTL_HSTFRM_OFFSET 2
203#define DWC2_GRSTCTL_INTKNQFLSH (1 << 3)
204#define DWC2_GRSTCTL_INTKNQFLSH_OFFSET 3
205#define DWC2_GRSTCTL_RXFFLSH (1 << 4)
206#define DWC2_GRSTCTL_RXFFLSH_OFFSET 4
207#define DWC2_GRSTCTL_TXFFLSH (1 << 5)
208#define DWC2_GRSTCTL_TXFFLSH_OFFSET 5
209#define DWC2_GRSTCTL_TXFNUM_MASK (0x1F << 6)
210#define DWC2_GRSTCTL_TXFNUM_OFFSET 6
211#define DWC2_GRSTCTL_DMAREQ (1 << 30)
212#define DWC2_GRSTCTL_DMAREQ_OFFSET 30
213#define DWC2_GRSTCTL_AHBIDLE (1 << 31)
214#define DWC2_GRSTCTL_AHBIDLE_OFFSET 31
215#define DWC2_GINTMSK_MODEMISMATCH (1 << 1)
216#define DWC2_GINTMSK_MODEMISMATCH_OFFSET 1
217#define DWC2_GINTMSK_OTGINTR (1 << 2)
218#define DWC2_GINTMSK_OTGINTR_OFFSET 2
219#define DWC2_GINTMSK_SOFINTR (1 << 3)
220#define DWC2_GINTMSK_SOFINTR_OFFSET 3
221#define DWC2_GINTMSK_RXSTSQLVL (1 << 4)
222#define DWC2_GINTMSK_RXSTSQLVL_OFFSET 4
223#define DWC2_GINTMSK_NPTXFEMPTY (1 << 5)
224#define DWC2_GINTMSK_NPTXFEMPTY_OFFSET 5
225#define DWC2_GINTMSK_GINNAKEFF (1 << 6)
226#define DWC2_GINTMSK_GINNAKEFF_OFFSET 6
227#define DWC2_GINTMSK_GOUTNAKEFF (1 << 7)
228#define DWC2_GINTMSK_GOUTNAKEFF_OFFSET 7
229#define DWC2_GINTMSK_I2CINTR (1 << 9)
230#define DWC2_GINTMSK_I2CINTR_OFFSET 9
231#define DWC2_GINTMSK_ERLYSUSPEND (1 << 10)
232#define DWC2_GINTMSK_ERLYSUSPEND_OFFSET 10
233#define DWC2_GINTMSK_USBSUSPEND (1 << 11)
234#define DWC2_GINTMSK_USBSUSPEND_OFFSET 11
235#define DWC2_GINTMSK_USBRESET (1 << 12)
236#define DWC2_GINTMSK_USBRESET_OFFSET 12
237#define DWC2_GINTMSK_ENUMDONE (1 << 13)
238#define DWC2_GINTMSK_ENUMDONE_OFFSET 13
239#define DWC2_GINTMSK_ISOOUTDROP (1 << 14)
240#define DWC2_GINTMSK_ISOOUTDROP_OFFSET 14
241#define DWC2_GINTMSK_EOPFRAME (1 << 15)
242#define DWC2_GINTMSK_EOPFRAME_OFFSET 15
243#define DWC2_GINTMSK_EPMISMATCH (1 << 17)
244#define DWC2_GINTMSK_EPMISMATCH_OFFSET 17
245#define DWC2_GINTMSK_INEPINTR (1 << 18)
246#define DWC2_GINTMSK_INEPINTR_OFFSET 18
247#define DWC2_GINTMSK_OUTEPINTR (1 << 19)
248#define DWC2_GINTMSK_OUTEPINTR_OFFSET 19
249#define DWC2_GINTMSK_INCOMPLISOIN (1 << 20)
250#define DWC2_GINTMSK_INCOMPLISOIN_OFFSET 20
251#define DWC2_GINTMSK_INCOMPLISOOUT (1 << 21)
252#define DWC2_GINTMSK_INCOMPLISOOUT_OFFSET 21
253#define DWC2_GINTMSK_PORTINTR (1 << 24)
254#define DWC2_GINTMSK_PORTINTR_OFFSET 24
255#define DWC2_GINTMSK_HCINTR (1 << 25)
256#define DWC2_GINTMSK_HCINTR_OFFSET 25
257#define DWC2_GINTMSK_PTXFEMPTY (1 << 26)
258#define DWC2_GINTMSK_PTXFEMPTY_OFFSET 26
259#define DWC2_GINTMSK_LPMTRANRCVD (1 << 27)
260#define DWC2_GINTMSK_LPMTRANRCVD_OFFSET 27
261#define DWC2_GINTMSK_CONIDSTSCHNG (1 << 28)
262#define DWC2_GINTMSK_CONIDSTSCHNG_OFFSET 28
263#define DWC2_GINTMSK_DISCONNECT (1 << 29)
264#define DWC2_GINTMSK_DISCONNECT_OFFSET 29
265#define DWC2_GINTMSK_SESSREQINTR (1 << 30)
266#define DWC2_GINTMSK_SESSREQINTR_OFFSET 30
267#define DWC2_GINTMSK_WKUPINTR (1 << 31)
268#define DWC2_GINTMSK_WKUPINTR_OFFSET 31
269#define DWC2_GINTSTS_CURMODE_DEVICE (0 << 0)
270#define DWC2_GINTSTS_CURMODE_HOST (1 << 0)
271#define DWC2_GINTSTS_CURMODE (1 << 0)
272#define DWC2_GINTSTS_CURMODE_OFFSET 0
273#define DWC2_GINTSTS_MODEMISMATCH (1 << 1)
274#define DWC2_GINTSTS_MODEMISMATCH_OFFSET 1
275#define DWC2_GINTSTS_OTGINTR (1 << 2)
276#define DWC2_GINTSTS_OTGINTR_OFFSET 2
277#define DWC2_GINTSTS_SOFINTR (1 << 3)
278#define DWC2_GINTSTS_SOFINTR_OFFSET 3
279#define DWC2_GINTSTS_RXSTSQLVL (1 << 4)
280#define DWC2_GINTSTS_RXSTSQLVL_OFFSET 4
281#define DWC2_GINTSTS_NPTXFEMPTY (1 << 5)
282#define DWC2_GINTSTS_NPTXFEMPTY_OFFSET 5
283#define DWC2_GINTSTS_GINNAKEFF (1 << 6)
284#define DWC2_GINTSTS_GINNAKEFF_OFFSET 6
285#define DWC2_GINTSTS_GOUTNAKEFF (1 << 7)
286#define DWC2_GINTSTS_GOUTNAKEFF_OFFSET 7
287#define DWC2_GINTSTS_I2CINTR (1 << 9)
288#define DWC2_GINTSTS_I2CINTR_OFFSET 9
289#define DWC2_GINTSTS_ERLYSUSPEND (1 << 10)
290#define DWC2_GINTSTS_ERLYSUSPEND_OFFSET 10
291#define DWC2_GINTSTS_USBSUSPEND (1 << 11)
292#define DWC2_GINTSTS_USBSUSPEND_OFFSET 11
293#define DWC2_GINTSTS_USBRESET (1 << 12)
294#define DWC2_GINTSTS_USBRESET_OFFSET 12
295#define DWC2_GINTSTS_ENUMDONE (1 << 13)
296#define DWC2_GINTSTS_ENUMDONE_OFFSET 13
297#define DWC2_GINTSTS_ISOOUTDROP (1 << 14)
298#define DWC2_GINTSTS_ISOOUTDROP_OFFSET 14
299#define DWC2_GINTSTS_EOPFRAME (1 << 15)
300#define DWC2_GINTSTS_EOPFRAME_OFFSET 15
301#define DWC2_GINTSTS_INTOKENRX (1 << 16)
302#define DWC2_GINTSTS_INTOKENRX_OFFSET 16
303#define DWC2_GINTSTS_EPMISMATCH (1 << 17)
304#define DWC2_GINTSTS_EPMISMATCH_OFFSET 17
305#define DWC2_GINTSTS_INEPINT (1 << 18)
306#define DWC2_GINTSTS_INEPINT_OFFSET 18
307#define DWC2_GINTSTS_OUTEPINTR (1 << 19)
308#define DWC2_GINTSTS_OUTEPINTR_OFFSET 19
309#define DWC2_GINTSTS_INCOMPLISOIN (1 << 20)
310#define DWC2_GINTSTS_INCOMPLISOIN_OFFSET 20
311#define DWC2_GINTSTS_INCOMPLISOOUT (1 << 21)
312#define DWC2_GINTSTS_INCOMPLISOOUT_OFFSET 21
313#define DWC2_GINTSTS_PORTINTR (1 << 24)
314#define DWC2_GINTSTS_PORTINTR_OFFSET 24
315#define DWC2_GINTSTS_HCINTR (1 << 25)
316#define DWC2_GINTSTS_HCINTR_OFFSET 25
317#define DWC2_GINTSTS_PTXFEMPTY (1 << 26)
318#define DWC2_GINTSTS_PTXFEMPTY_OFFSET 26
319#define DWC2_GINTSTS_LPMTRANRCVD (1 << 27)
320#define DWC2_GINTSTS_LPMTRANRCVD_OFFSET 27
321#define DWC2_GINTSTS_CONIDSTSCHNG (1 << 28)
322#define DWC2_GINTSTS_CONIDSTSCHNG_OFFSET 28
323#define DWC2_GINTSTS_DISCONNECT (1 << 29)
324#define DWC2_GINTSTS_DISCONNECT_OFFSET 29
325#define DWC2_GINTSTS_SESSREQINTR (1 << 30)
326#define DWC2_GINTSTS_SESSREQINTR_OFFSET 30
327#define DWC2_GINTSTS_WKUPINTR (1 << 31)
328#define DWC2_GINTSTS_WKUPINTR_OFFSET 31
329#define DWC2_GRXSTS_EPNUM_MASK (0xF << 0)
330#define DWC2_GRXSTS_EPNUM_OFFSET 0
331#define DWC2_GRXSTS_BCNT_MASK (0x7FF << 4)
332#define DWC2_GRXSTS_BCNT_OFFSET 4
333#define DWC2_GRXSTS_DPID_MASK (0x3 << 15)
334#define DWC2_GRXSTS_DPID_OFFSET 15
335#define DWC2_GRXSTS_PKTSTS_MASK (0xF << 17)
336#define DWC2_GRXSTS_PKTSTS_OFFSET 17
337#define DWC2_GRXSTS_FN_MASK (0xF << 21)
338#define DWC2_GRXSTS_FN_OFFSET 21
339#define DWC2_FIFOSIZE_STARTADDR_MASK (0xFFFF << 0)
340#define DWC2_FIFOSIZE_STARTADDR_OFFSET 0
341#define DWC2_FIFOSIZE_DEPTH_MASK (0xFFFF << 16)
342#define DWC2_FIFOSIZE_DEPTH_OFFSET 16
343#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK (0xFFFF << 0)
344#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_OFFSET 0
345#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK (0xFF << 16)
346#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_OFFSET 16
347#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE (1 << 24)
348#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE_OFFSET 24
349#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK (0x3 << 25)
350#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_OFFSET 25
351#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK (0xF << 27)
352#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_OFFSET 27
353#define DWC2_DTXFSTS_TXFSPCAVAIL_MASK (0xFFFF << 0)
354#define DWC2_DTXFSTS_TXFSPCAVAIL_OFFSET 0
355#define DWC2_GI2CCTL_RWDATA_MASK (0xFF << 0)
356#define DWC2_GI2CCTL_RWDATA_OFFSET 0
357#define DWC2_GI2CCTL_REGADDR_MASK (0xFF << 8)
358#define DWC2_GI2CCTL_REGADDR_OFFSET 8
359#define DWC2_GI2CCTL_ADDR_MASK (0x7F << 16)
360#define DWC2_GI2CCTL_ADDR_OFFSET 16
361#define DWC2_GI2CCTL_I2CEN (1 << 23)
362#define DWC2_GI2CCTL_I2CEN_OFFSET 23
363#define DWC2_GI2CCTL_ACK (1 << 24)
364#define DWC2_GI2CCTL_ACK_OFFSET 24
365#define DWC2_GI2CCTL_I2CSUSPCTL (1 << 25)
366#define DWC2_GI2CCTL_I2CSUSPCTL_OFFSET 25
367#define DWC2_GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
368#define DWC2_GI2CCTL_I2CDEVADDR_OFFSET 26
369#define DWC2_GI2CCTL_RW (1 << 30)
370#define DWC2_GI2CCTL_RW_OFFSET 30
371#define DWC2_GI2CCTL_BSYDNE (1 << 31)
372#define DWC2_GI2CCTL_BSYDNE_OFFSET 31
373#define DWC2_HWCFG1_EP_DIR0_MASK (0x3 << 0)
374#define DWC2_HWCFG1_EP_DIR0_OFFSET 0
375#define DWC2_HWCFG1_EP_DIR1_MASK (0x3 << 2)
376#define DWC2_HWCFG1_EP_DIR1_OFFSET 2
377#define DWC2_HWCFG1_EP_DIR2_MASK (0x3 << 4)
378#define DWC2_HWCFG1_EP_DIR2_OFFSET 4
379#define DWC2_HWCFG1_EP_DIR3_MASK (0x3 << 6)
380#define DWC2_HWCFG1_EP_DIR3_OFFSET 6
381#define DWC2_HWCFG1_EP_DIR4_MASK (0x3 << 8)
382#define DWC2_HWCFG1_EP_DIR4_OFFSET 8
383#define DWC2_HWCFG1_EP_DIR5_MASK (0x3 << 10)
384#define DWC2_HWCFG1_EP_DIR5_OFFSET 10
385#define DWC2_HWCFG1_EP_DIR6_MASK (0x3 << 12)
386#define DWC2_HWCFG1_EP_DIR6_OFFSET 12
387#define DWC2_HWCFG1_EP_DIR7_MASK (0x3 << 14)
388#define DWC2_HWCFG1_EP_DIR7_OFFSET 14
389#define DWC2_HWCFG1_EP_DIR8_MASK (0x3 << 16)
390#define DWC2_HWCFG1_EP_DIR8_OFFSET 16
391#define DWC2_HWCFG1_EP_DIR9_MASK (0x3 << 18)
392#define DWC2_HWCFG1_EP_DIR9_OFFSET 18
393#define DWC2_HWCFG1_EP_DIR10_MASK (0x3 << 20)
394#define DWC2_HWCFG1_EP_DIR10_OFFSET 20
395#define DWC2_HWCFG1_EP_DIR11_MASK (0x3 << 22)
396#define DWC2_HWCFG1_EP_DIR11_OFFSET 22
397#define DWC2_HWCFG1_EP_DIR12_MASK (0x3 << 24)
398#define DWC2_HWCFG1_EP_DIR12_OFFSET 24
399#define DWC2_HWCFG1_EP_DIR13_MASK (0x3 << 26)
400#define DWC2_HWCFG1_EP_DIR13_OFFSET 26
401#define DWC2_HWCFG1_EP_DIR14_MASK (0x3 << 28)
402#define DWC2_HWCFG1_EP_DIR14_OFFSET 28
403#define DWC2_HWCFG1_EP_DIR15_MASK (0x3 << 30)
404#define DWC2_HWCFG1_EP_DIR15_OFFSET 30
405#define DWC2_HWCFG2_OP_MODE_MASK (0x7 << 0)
406#define DWC2_HWCFG2_OP_MODE_OFFSET 0
407#define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY (0x0 << 3)
408#define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA (0x1 << 3)
409#define DWC2_HWCFG2_ARCHITECTURE_INT_DMA (0x2 << 3)
410#define DWC2_HWCFG2_ARCHITECTURE_MASK (0x3 << 3)
411#define DWC2_HWCFG2_ARCHITECTURE_OFFSET 3
412#define DWC2_HWCFG2_POINT2POINT (1 << 5)
413#define DWC2_HWCFG2_POINT2POINT_OFFSET 5
414#define DWC2_HWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
415#define DWC2_HWCFG2_HS_PHY_TYPE_OFFSET 6
416#define DWC2_HWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
417#define DWC2_HWCFG2_FS_PHY_TYPE_OFFSET 8
418#define DWC2_HWCFG2_NUM_DEV_EP_MASK (0xF << 10)
419#define DWC2_HWCFG2_NUM_DEV_EP_OFFSET 10
420#define DWC2_HWCFG2_NUM_HOST_CHAN_MASK (0xF << 14)
421#define DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET 14
422#define DWC2_HWCFG2_PERIO_EP_SUPPORTED (1 << 18)
423#define DWC2_HWCFG2_PERIO_EP_SUPPORTED_OFFSET 18
424#define DWC2_HWCFG2_DYNAMIC_FIFO (1 << 19)
425#define DWC2_HWCFG2_DYNAMIC_FIFO_OFFSET 19
426#define DWC2_HWCFG2_MULTI_PROC_INT (1 << 20)
427#define DWC2_HWCFG2_MULTI_PROC_INT_OFFSET 20
428#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
429#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_OFFSET 22
430#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
431#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_OFFSET 24
432#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1F << 26)
433#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_OFFSET 26
434#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xF << 0)
435#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_OFFSET 0
436#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
437#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_OFFSET 4
438#define DWC2_HWCFG3_OTG_FUNC (1 << 7)
439#define DWC2_HWCFG3_OTG_FUNC_OFFSET 7
440#define DWC2_HWCFG3_I2C (1 << 8)
441#define DWC2_HWCFG3_I2C_OFFSET 8
442#define DWC2_HWCFG3_VENDOR_CTRL_IF (1 << 9)
443#define DWC2_HWCFG3_VENDOR_CTRL_IF_OFFSET 9
444#define DWC2_HWCFG3_OPTIONAL_FEATURES (1 << 10)
445#define DWC2_HWCFG3_OPTIONAL_FEATURES_OFFSET 10
446#define DWC2_HWCFG3_SYNCH_RESET_TYPE (1 << 11)
447#define DWC2_HWCFG3_SYNCH_RESET_TYPE_OFFSET 11
448#define DWC2_HWCFG3_OTG_ENABLE_IC_USB (1 << 12)
449#define DWC2_HWCFG3_OTG_ENABLE_IC_USB_OFFSET 12
450#define DWC2_HWCFG3_OTG_ENABLE_HSIC (1 << 13)
451#define DWC2_HWCFG3_OTG_ENABLE_HSIC_OFFSET 13
452#define DWC2_HWCFG3_OTG_LPM_EN (1 << 15)
453#define DWC2_HWCFG3_OTG_LPM_EN_OFFSET 15
454#define DWC2_HWCFG3_DFIFO_DEPTH_MASK (0xFFFF << 16)
455#define DWC2_HWCFG3_DFIFO_DEPTH_OFFSET 16
456#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xF << 0)
457#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_OFFSET 0
458#define DWC2_HWCFG4_POWER_OPTIMIZ (1 << 4)
459#define DWC2_HWCFG4_POWER_OPTIMIZ_OFFSET 4
460#define DWC2_HWCFG4_MIN_AHB_FREQ_MASK (0x1FF << 5)
461#define DWC2_HWCFG4_MIN_AHB_FREQ_OFFSET 5
462#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
463#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_OFFSET 14
464#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xF << 16)
465#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_OFFSET 16
466#define DWC2_HWCFG4_IDDIG_FILT_EN (1 << 20)
467#define DWC2_HWCFG4_IDDIG_FILT_EN_OFFSET 20
468#define DWC2_HWCFG4_VBUS_VALID_FILT_EN (1 << 21)
469#define DWC2_HWCFG4_VBUS_VALID_FILT_EN_OFFSET 21
470#define DWC2_HWCFG4_A_VALID_FILT_EN (1 << 22)
471#define DWC2_HWCFG4_A_VALID_FILT_EN_OFFSET 22
472#define DWC2_HWCFG4_B_VALID_FILT_EN (1 << 23)
473#define DWC2_HWCFG4_B_VALID_FILT_EN_OFFSET 23
474#define DWC2_HWCFG4_SESSION_END_FILT_EN (1 << 24)
475#define DWC2_HWCFG4_SESSION_END_FILT_EN_OFFSET 24
476#define DWC2_HWCFG4_DED_FIFO_EN (1 << 25)
477#define DWC2_HWCFG4_DED_FIFO_EN_OFFSET 25
478#define DWC2_HWCFG4_NUM_IN_EPS_MASK (0xF << 26)
479#define DWC2_HWCFG4_NUM_IN_EPS_OFFSET 26
480#define DWC2_HWCFG4_DESC_DMA (1 << 30)
481#define DWC2_HWCFG4_DESC_DMA_OFFSET 30
482#define DWC2_HWCFG4_DESC_DMA_DYN (1 << 31)
483#define DWC2_HWCFG4_DESC_DMA_DYN_OFFSET 31
484#define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ 0
485#define DWC2_HCFG_FSLSPCLKSEL_48_MHZ 1
486#define DWC2_HCFG_FSLSPCLKSEL_6_MHZ 2
487#define DWC2_HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
488#define DWC2_HCFG_FSLSPCLKSEL_OFFSET 0
489#define DWC2_HCFG_FSLSSUPP (1 << 2)
490#define DWC2_HCFG_FSLSSUPP_OFFSET 2
491#define DWC2_HCFG_DESCDMA (1 << 23)
492#define DWC2_HCFG_DESCDMA_OFFSET 23
493#define DWC2_HCFG_FRLISTEN_MASK (0x3 << 24)
494#define DWC2_HCFG_FRLISTEN_OFFSET 24
495#define DWC2_HCFG_PERSCHEDENA (1 << 26)
496#define DWC2_HCFG_PERSCHEDENA_OFFSET 26
497#define DWC2_HCFG_PERSCHEDSTAT (1 << 27)
498#define DWC2_HCFG_PERSCHEDSTAT_OFFSET 27
499#define DWC2_HFIR_FRINT_MASK (0xFFFF << 0)
500#define DWC2_HFIR_FRINT_OFFSET 0
501#define DWC2_HFNUM_FRNUM_MASK (0xFFFF << 0)
502#define DWC2_HFNUM_FRNUM_OFFSET 0
503#define DWC2_HFNUM_FRREM_MASK (0xFFFF << 16)
504#define DWC2_HFNUM_FRREM_OFFSET 16
Stefan Brünsd2ff51b2016-01-17 04:09:56 +0100505#define DWC2_HFNUM_MAX_FRNUM 0x3FFF
Oleksandr Tymoshenko6e9e0622014-02-01 21:51:25 -0700506#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK (0xFFFF << 0)
507#define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET 0
508#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK (0xFF << 16)
509#define DWC2_HPTXSTS_PTXQSPCAVAIL_OFFSET 16
510#define DWC2_HPTXSTS_PTXQTOP_TERMINATE (1 << 24)
511#define DWC2_HPTXSTS_PTXQTOP_TERMINATE_OFFSET 24
512#define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK (0x3 << 25)
513#define DWC2_HPTXSTS_PTXQTOP_TOKEN_OFFSET 25
514#define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK (0xF << 27)
515#define DWC2_HPTXSTS_PTXQTOP_CHNUM_OFFSET 27
516#define DWC2_HPTXSTS_PTXQTOP_ODD (1 << 31)
517#define DWC2_HPTXSTS_PTXQTOP_ODD_OFFSET 31
518#define DWC2_HPRT0_PRTCONNSTS (1 << 0)
519#define DWC2_HPRT0_PRTCONNSTS_OFFSET 0
520#define DWC2_HPRT0_PRTCONNDET (1 << 1)
521#define DWC2_HPRT0_PRTCONNDET_OFFSET 1
522#define DWC2_HPRT0_PRTENA (1 << 2)
523#define DWC2_HPRT0_PRTENA_OFFSET 2
524#define DWC2_HPRT0_PRTENCHNG (1 << 3)
525#define DWC2_HPRT0_PRTENCHNG_OFFSET 3
526#define DWC2_HPRT0_PRTOVRCURRACT (1 << 4)
527#define DWC2_HPRT0_PRTOVRCURRACT_OFFSET 4
528#define DWC2_HPRT0_PRTOVRCURRCHNG (1 << 5)
529#define DWC2_HPRT0_PRTOVRCURRCHNG_OFFSET 5
530#define DWC2_HPRT0_PRTRES (1 << 6)
531#define DWC2_HPRT0_PRTRES_OFFSET 6
532#define DWC2_HPRT0_PRTSUSP (1 << 7)
533#define DWC2_HPRT0_PRTSUSP_OFFSET 7
534#define DWC2_HPRT0_PRTRST (1 << 8)
535#define DWC2_HPRT0_PRTRST_OFFSET 8
536#define DWC2_HPRT0_PRTLNSTS_MASK (0x3 << 10)
537#define DWC2_HPRT0_PRTLNSTS_OFFSET 10
538#define DWC2_HPRT0_PRTPWR (1 << 12)
539#define DWC2_HPRT0_PRTPWR_OFFSET 12
540#define DWC2_HPRT0_PRTTSTCTL_MASK (0xF << 13)
541#define DWC2_HPRT0_PRTTSTCTL_OFFSET 13
Stephen Warren4748cce2015-03-27 21:55:38 -0600542#define DWC2_HPRT0_PRTSPD_HIGH (0 << 17)
543#define DWC2_HPRT0_PRTSPD_FULL (1 << 17)
544#define DWC2_HPRT0_PRTSPD_LOW (2 << 17)
Oleksandr Tymoshenko6e9e0622014-02-01 21:51:25 -0700545#define DWC2_HPRT0_PRTSPD_MASK (0x3 << 17)
546#define DWC2_HPRT0_PRTSPD_OFFSET 17
547#define DWC2_HAINT_CH0 (1 << 0)
548#define DWC2_HAINT_CH0_OFFSET 0
549#define DWC2_HAINT_CH1 (1 << 1)
550#define DWC2_HAINT_CH1_OFFSET 1
551#define DWC2_HAINT_CH2 (1 << 2)
552#define DWC2_HAINT_CH2_OFFSET 2
553#define DWC2_HAINT_CH3 (1 << 3)
554#define DWC2_HAINT_CH3_OFFSET 3
555#define DWC2_HAINT_CH4 (1 << 4)
556#define DWC2_HAINT_CH4_OFFSET 4
557#define DWC2_HAINT_CH5 (1 << 5)
558#define DWC2_HAINT_CH5_OFFSET 5
559#define DWC2_HAINT_CH6 (1 << 6)
560#define DWC2_HAINT_CH6_OFFSET 6
561#define DWC2_HAINT_CH7 (1 << 7)
562#define DWC2_HAINT_CH7_OFFSET 7
563#define DWC2_HAINT_CH8 (1 << 8)
564#define DWC2_HAINT_CH8_OFFSET 8
565#define DWC2_HAINT_CH9 (1 << 9)
566#define DWC2_HAINT_CH9_OFFSET 9
567#define DWC2_HAINT_CH10 (1 << 10)
568#define DWC2_HAINT_CH10_OFFSET 10
569#define DWC2_HAINT_CH11 (1 << 11)
570#define DWC2_HAINT_CH11_OFFSET 11
571#define DWC2_HAINT_CH12 (1 << 12)
572#define DWC2_HAINT_CH12_OFFSET 12
573#define DWC2_HAINT_CH13 (1 << 13)
574#define DWC2_HAINT_CH13_OFFSET 13
575#define DWC2_HAINT_CH14 (1 << 14)
576#define DWC2_HAINT_CH14_OFFSET 14
577#define DWC2_HAINT_CH15 (1 << 15)
578#define DWC2_HAINT_CH15_OFFSET 15
579#define DWC2_HAINT_CHINT_MASK 0xffff
580#define DWC2_HAINT_CHINT_OFFSET 0
581#define DWC2_HAINTMSK_CH0 (1 << 0)
582#define DWC2_HAINTMSK_CH0_OFFSET 0
583#define DWC2_HAINTMSK_CH1 (1 << 1)
584#define DWC2_HAINTMSK_CH1_OFFSET 1
585#define DWC2_HAINTMSK_CH2 (1 << 2)
586#define DWC2_HAINTMSK_CH2_OFFSET 2
587#define DWC2_HAINTMSK_CH3 (1 << 3)
588#define DWC2_HAINTMSK_CH3_OFFSET 3
589#define DWC2_HAINTMSK_CH4 (1 << 4)
590#define DWC2_HAINTMSK_CH4_OFFSET 4
591#define DWC2_HAINTMSK_CH5 (1 << 5)
592#define DWC2_HAINTMSK_CH5_OFFSET 5
593#define DWC2_HAINTMSK_CH6 (1 << 6)
594#define DWC2_HAINTMSK_CH6_OFFSET 6
595#define DWC2_HAINTMSK_CH7 (1 << 7)
596#define DWC2_HAINTMSK_CH7_OFFSET 7
597#define DWC2_HAINTMSK_CH8 (1 << 8)
598#define DWC2_HAINTMSK_CH8_OFFSET 8
599#define DWC2_HAINTMSK_CH9 (1 << 9)
600#define DWC2_HAINTMSK_CH9_OFFSET 9
601#define DWC2_HAINTMSK_CH10 (1 << 10)
602#define DWC2_HAINTMSK_CH10_OFFSET 10
603#define DWC2_HAINTMSK_CH11 (1 << 11)
604#define DWC2_HAINTMSK_CH11_OFFSET 11
605#define DWC2_HAINTMSK_CH12 (1 << 12)
606#define DWC2_HAINTMSK_CH12_OFFSET 12
607#define DWC2_HAINTMSK_CH13 (1 << 13)
608#define DWC2_HAINTMSK_CH13_OFFSET 13
609#define DWC2_HAINTMSK_CH14 (1 << 14)
610#define DWC2_HAINTMSK_CH14_OFFSET 14
611#define DWC2_HAINTMSK_CH15 (1 << 15)
612#define DWC2_HAINTMSK_CH15_OFFSET 15
613#define DWC2_HAINTMSK_CHINT_MASK 0xffff
614#define DWC2_HAINTMSK_CHINT_OFFSET 0
615#define DWC2_HCCHAR_MPS_MASK (0x7FF << 0)
616#define DWC2_HCCHAR_MPS_OFFSET 0
617#define DWC2_HCCHAR_EPNUM_MASK (0xF << 11)
618#define DWC2_HCCHAR_EPNUM_OFFSET 11
619#define DWC2_HCCHAR_EPDIR (1 << 15)
620#define DWC2_HCCHAR_EPDIR_OFFSET 15
621#define DWC2_HCCHAR_LSPDDEV (1 << 17)
622#define DWC2_HCCHAR_LSPDDEV_OFFSET 17
623#define DWC2_HCCHAR_EPTYPE_CONTROL 0
624#define DWC2_HCCHAR_EPTYPE_ISOC 1
625#define DWC2_HCCHAR_EPTYPE_BULK 2
626#define DWC2_HCCHAR_EPTYPE_INTR 3
627#define DWC2_HCCHAR_EPTYPE_MASK (0x3 << 18)
628#define DWC2_HCCHAR_EPTYPE_OFFSET 18
629#define DWC2_HCCHAR_MULTICNT_MASK (0x3 << 20)
630#define DWC2_HCCHAR_MULTICNT_OFFSET 20
631#define DWC2_HCCHAR_DEVADDR_MASK (0x7F << 22)
632#define DWC2_HCCHAR_DEVADDR_OFFSET 22
633#define DWC2_HCCHAR_ODDFRM (1 << 29)
634#define DWC2_HCCHAR_ODDFRM_OFFSET 29
635#define DWC2_HCCHAR_CHDIS (1 << 30)
636#define DWC2_HCCHAR_CHDIS_OFFSET 30
637#define DWC2_HCCHAR_CHEN (1 << 31)
638#define DWC2_HCCHAR_CHEN_OFFSET 31
639#define DWC2_HCSPLT_PRTADDR_MASK (0x7F << 0)
640#define DWC2_HCSPLT_PRTADDR_OFFSET 0
641#define DWC2_HCSPLT_HUBADDR_MASK (0x7F << 7)
642#define DWC2_HCSPLT_HUBADDR_OFFSET 7
643#define DWC2_HCSPLT_XACTPOS_MASK (0x3 << 14)
644#define DWC2_HCSPLT_XACTPOS_OFFSET 14
645#define DWC2_HCSPLT_COMPSPLT (1 << 16)
646#define DWC2_HCSPLT_COMPSPLT_OFFSET 16
647#define DWC2_HCSPLT_SPLTENA (1 << 31)
648#define DWC2_HCSPLT_SPLTENA_OFFSET 31
649#define DWC2_HCINT_XFERCOMP (1 << 0)
650#define DWC2_HCINT_XFERCOMP_OFFSET 0
651#define DWC2_HCINT_CHHLTD (1 << 1)
652#define DWC2_HCINT_CHHLTD_OFFSET 1
653#define DWC2_HCINT_AHBERR (1 << 2)
654#define DWC2_HCINT_AHBERR_OFFSET 2
655#define DWC2_HCINT_STALL (1 << 3)
656#define DWC2_HCINT_STALL_OFFSET 3
657#define DWC2_HCINT_NAK (1 << 4)
658#define DWC2_HCINT_NAK_OFFSET 4
659#define DWC2_HCINT_ACK (1 << 5)
660#define DWC2_HCINT_ACK_OFFSET 5
661#define DWC2_HCINT_NYET (1 << 6)
662#define DWC2_HCINT_NYET_OFFSET 6
663#define DWC2_HCINT_XACTERR (1 << 7)
664#define DWC2_HCINT_XACTERR_OFFSET 7
665#define DWC2_HCINT_BBLERR (1 << 8)
666#define DWC2_HCINT_BBLERR_OFFSET 8
667#define DWC2_HCINT_FRMOVRUN (1 << 9)
668#define DWC2_HCINT_FRMOVRUN_OFFSET 9
669#define DWC2_HCINT_DATATGLERR (1 << 10)
670#define DWC2_HCINT_DATATGLERR_OFFSET 10
671#define DWC2_HCINT_BNA (1 << 11)
672#define DWC2_HCINT_BNA_OFFSET 11
673#define DWC2_HCINT_XCS_XACT (1 << 12)
674#define DWC2_HCINT_XCS_XACT_OFFSET 12
675#define DWC2_HCINT_FRM_LIST_ROLL (1 << 13)
676#define DWC2_HCINT_FRM_LIST_ROLL_OFFSET 13
677#define DWC2_HCINTMSK_XFERCOMPL (1 << 0)
678#define DWC2_HCINTMSK_XFERCOMPL_OFFSET 0
679#define DWC2_HCINTMSK_CHHLTD (1 << 1)
680#define DWC2_HCINTMSK_CHHLTD_OFFSET 1
681#define DWC2_HCINTMSK_AHBERR (1 << 2)
682#define DWC2_HCINTMSK_AHBERR_OFFSET 2
683#define DWC2_HCINTMSK_STALL (1 << 3)
684#define DWC2_HCINTMSK_STALL_OFFSET 3
685#define DWC2_HCINTMSK_NAK (1 << 4)
686#define DWC2_HCINTMSK_NAK_OFFSET 4
687#define DWC2_HCINTMSK_ACK (1 << 5)
688#define DWC2_HCINTMSK_ACK_OFFSET 5
689#define DWC2_HCINTMSK_NYET (1 << 6)
690#define DWC2_HCINTMSK_NYET_OFFSET 6
691#define DWC2_HCINTMSK_XACTERR (1 << 7)
692#define DWC2_HCINTMSK_XACTERR_OFFSET 7
693#define DWC2_HCINTMSK_BBLERR (1 << 8)
694#define DWC2_HCINTMSK_BBLERR_OFFSET 8
695#define DWC2_HCINTMSK_FRMOVRUN (1 << 9)
696#define DWC2_HCINTMSK_FRMOVRUN_OFFSET 9
697#define DWC2_HCINTMSK_DATATGLERR (1 << 10)
698#define DWC2_HCINTMSK_DATATGLERR_OFFSET 10
699#define DWC2_HCINTMSK_BNA (1 << 11)
700#define DWC2_HCINTMSK_BNA_OFFSET 11
701#define DWC2_HCINTMSK_XCS_XACT (1 << 12)
702#define DWC2_HCINTMSK_XCS_XACT_OFFSET 12
703#define DWC2_HCINTMSK_FRM_LIST_ROLL (1 << 13)
704#define DWC2_HCINTMSK_FRM_LIST_ROLL_OFFSET 13
705#define DWC2_HCTSIZ_XFERSIZE_MASK 0x7ffff
706#define DWC2_HCTSIZ_XFERSIZE_OFFSET 0
707#define DWC2_HCTSIZ_SCHINFO_MASK 0xff
708#define DWC2_HCTSIZ_SCHINFO_OFFSET 0
709#define DWC2_HCTSIZ_NTD_MASK (0xff << 8)
710#define DWC2_HCTSIZ_NTD_OFFSET 8
711#define DWC2_HCTSIZ_PKTCNT_MASK (0x3ff << 19)
712#define DWC2_HCTSIZ_PKTCNT_OFFSET 19
713#define DWC2_HCTSIZ_PID_MASK (0x3 << 29)
714#define DWC2_HCTSIZ_PID_OFFSET 29
715#define DWC2_HCTSIZ_DOPNG (1 << 31)
716#define DWC2_HCTSIZ_DOPNG_OFFSET 31
717#define DWC2_HCDMA_CTD_MASK (0xFF << 3)
718#define DWC2_HCDMA_CTD_OFFSET 3
719#define DWC2_HCDMA_DMA_ADDR_MASK (0x1FFFFF << 11)
720#define DWC2_HCDMA_DMA_ADDR_OFFSET 11
721#define DWC2_PCGCCTL_STOPPCLK (1 << 0)
722#define DWC2_PCGCCTL_STOPPCLK_OFFSET 0
723#define DWC2_PCGCCTL_GATEHCLK (1 << 1)
724#define DWC2_PCGCCTL_GATEHCLK_OFFSET 1
725#define DWC2_PCGCCTL_PWRCLMP (1 << 2)
726#define DWC2_PCGCCTL_PWRCLMP_OFFSET 2
727#define DWC2_PCGCCTL_RSTPDWNMODULE (1 << 3)
728#define DWC2_PCGCCTL_RSTPDWNMODULE_OFFSET 3
729#define DWC2_PCGCCTL_PHYSUSPENDED (1 << 4)
730#define DWC2_PCGCCTL_PHYSUSPENDED_OFFSET 4
731#define DWC2_PCGCCTL_ENBL_SLEEP_GATING (1 << 5)
732#define DWC2_PCGCCTL_ENBL_SLEEP_GATING_OFFSET 5
733#define DWC2_PCGCCTL_PHY_IN_SLEEP (1 << 6)
734#define DWC2_PCGCCTL_PHY_IN_SLEEP_OFFSET 6
735#define DWC2_PCGCCTL_DEEP_SLEEP (1 << 7)
736#define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET 7
737#define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12)
Peter Griffin5cfd6c02015-05-12 14:38:27 +0100738#define DWC2_SNPSID_DEVID_VER_3xx (0x4f543 << 12)
Oleksandr Tymoshenko6e9e0622014-02-01 21:51:25 -0700739#define DWC2_SNPSID_DEVID_MASK (0xfffff << 12)
740#define DWC2_SNPSID_DEVID_OFFSET 12
741
742/* Host controller specific */
743#define DWC2_HC_PID_DATA0 0
744#define DWC2_HC_PID_DATA2 1
745#define DWC2_HC_PID_DATA1 2
746#define DWC2_HC_PID_MDATA 3
747#define DWC2_HC_PID_SETUP 3
748
749/* roothub.a masks */
750#define RH_A_NDP (0xff << 0) /* number of downstream ports */
751#define RH_A_PSM (1 << 8) /* power switching mode */
752#define RH_A_NPS (1 << 9) /* no power switching */
753#define RH_A_DT (1 << 10) /* device type (mbz) */
754#define RH_A_OCPM (1 << 11) /* over current protection mode */
755#define RH_A_NOCP (1 << 12) /* no over current protection */
756#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
757
758/* roothub.b masks */
759#define RH_B_DR 0x0000ffff /* device removable flags */
760#define RH_B_PPCM 0xffff0000 /* port power control mask */
761
762/* Default driver configuration */
763#define CONFIG_DWC2_DMA_ENABLE
764#define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */
765#undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */
766#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */
767#define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */
768#define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS)
769#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */
770#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */
771#define CONFIG_DWC2_MAX_TRANSFER_SIZE 65535
772#define CONFIG_DWC2_MAX_PACKET_COUNT 511
773
774#define DWC2_PHY_TYPE_FS 0
775#define DWC2_PHY_TYPE_UTMI 1
776#define DWC2_PHY_TYPE_ULPI 2
777#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */
778#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */
779
780#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */
781#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */
782#undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */
783#undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */
784#undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */
785#undef CONFIG_DWC2_THR_CTL /* Threshold control */
786#define CONFIG_DWC2_TX_THR_LENGTH 64
787#undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */
788
789#endif /* __DWC2_H__ */