blob: 7b1118138884b4a36ff46fac7f88cc512e2b3bfc [file] [log] [blame]
Stefano Babic01bb24b2011-01-19 22:46:29 +00001/*
2 * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de>
3 *
4 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Stefano Babic01bb24b2011-01-19 22:46:29 +00007 */
8
9#ifndef __ASM_ARCH_MC9SDZ60_H
10#define __ASM_ARCH_MC9SDZ60_H
11
12/**
13 * Register addresses for the MC9SDZ60
14 *
15 * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h
16 * but not include/linux/mfd/mc9s08dz60/pmic.h
17 *
18 */
19enum mc9sdz60_reg {
20 MC9SDZ60_REG_VERSION = 0x00,
21 /* reserved 0x01 */
22 MC9SDZ60_REG_SECS = 0x02,
23 MC9SDZ60_REG_MINS = 0x03,
24 MC9SDZ60_REG_HRS = 0x04,
25 MC9SDZ60_REG_DAY = 0x05,
26 MC9SDZ60_REG_DATE = 0x06,
27 MC9SDZ60_REG_MONTH = 0x07,
28 MC9SDZ60_REG_YEAR = 0x08,
29 MC9SDZ60_REG_ALARM_SECS = 0x09,
30 MC9SDZ60_REG_ALARM_MINS = 0x0a,
31 MC9SDZ60_REG_ALARM_HRS = 0x0b,
32 /* reserved 0x0c */
33 /* reserved 0x0d */
34 MC9SDZ60_REG_TS_CONTROL = 0x0e,
35 MC9SDZ60_REG_X_LOW = 0x0f,
36 MC9SDZ60_REG_Y_LOW = 0x10,
37 MC9SDZ60_REG_XY_HIGH = 0x11,
38 MC9SDZ60_REG_X_LEFT_LOW = 0x12,
39 MC9SDZ60_REG_X_LEFT_HIGH = 0x13,
40 MC9SDZ60_REG_X_RIGHT = 0x14,
41 MC9SDZ60_REG_Y_TOP_LOW = 0x15,
42 MC9SDZ60_REG_Y_TOP_HIGH = 0x16,
43 MC9SDZ60_REG_Y_BOTTOM = 0x17,
44 /* reserved 0x18 */
45 /* reserved 0x19 */
46 MC9SDZ60_REG_RESET_1 = 0x1a,
47 MC9SDZ60_REG_RESET_2 = 0x1b,
48 MC9SDZ60_REG_POWER_CTL = 0x1c,
49 MC9SDZ60_REG_DELAY_CONFIG = 0x1d,
50 /* reserved 0x1e */
51 /* reserved 0x1f */
52 MC9SDZ60_REG_GPIO_1 = 0x20,
53 MC9SDZ60_REG_GPIO_2 = 0x21,
54 MC9SDZ60_REG_KPD_1 = 0x22,
55 MC9SDZ60_REG_KPD_2 = 0x23,
56 MC9SDZ60_REG_KPD_CONTROL = 0x24,
57 MC9SDZ60_REG_INT_ENABLE_1 = 0x25,
58 MC9SDZ60_REG_INT_ENABLE_2 = 0x26,
59 MC9SDZ60_REG_INT_FLAG_1 = 0x27,
60 MC9SDZ60_REG_INT_FLAG_2 = 0x28,
61 MC9SDZ60_REG_DES_FLAG = 0x29,
62};
63
64extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg);
65extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val);
66
67#endif /* __ASM_ARCH_MC9SDZ60_H */