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wdenkaffae2b2002-08-17 09:36:01 +00001/*
wdenk04a85b32004-04-15 18:22:41 +00002 * (C) Copyright 2000-2004
wdenkaffae2b2002-08-17 09:36:01 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkaffae2b2002-08-17 09:36:01 +00006 */
7
8#ifndef _PCMCIA_H
9#define _PCMCIA_H
10
11#include <common.h>
12#include <config.h>
13
14/*
15 * Allow configuration to select PCMCIA slot,
16 * or try to generate a useful default
17 */
Heiko Schocher5b8e76c2017-06-07 17:33:09 +020018#if defined(CONFIG_CMD_PCMCIA)
wdenkaffae2b2002-08-17 09:36:01 +000019
20#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
wdenkaffae2b2002-08-17 09:36:01 +000021# error "PCMCIA Slot not configured"
wdenkaffae2b2002-08-17 09:36:01 +000022#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
23
24/* Make sure exactly one slot is defined - we support only one for now */
25#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
26#error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
27#endif
28#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
29#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
30#endif
31
wdenkea909b72002-11-21 23:11:29 +000032#ifndef PCMCIA_SOCKETS_NO
wdenkaffae2b2002-08-17 09:36:01 +000033#define PCMCIA_SOCKETS_NO 1
wdenkea909b72002-11-21 23:11:29 +000034#endif
35#ifndef PCMCIA_MEM_WIN_NO
wdenkaffae2b2002-08-17 09:36:01 +000036#define PCMCIA_MEM_WIN_NO 4
wdenkea909b72002-11-21 23:11:29 +000037#endif
wdenkaffae2b2002-08-17 09:36:01 +000038#define PCMCIA_IO_WIN_NO 2
39
40/* define _slot_ to be able to optimize macros */
41#ifdef CONFIG_PCMCIA_SLOT_A
42# define _slot_ 0
43# define PCMCIA_SLOT_MSG "slot A"
44# define PCMCIA_SLOT_x PCMCIA_PSLOT_A
45#else
46# define _slot_ 1
47# define PCMCIA_SLOT_MSG "slot B"
48# define PCMCIA_SLOT_x PCMCIA_PSLOT_B
49#endif
50
51/*
wdenkaffae2b2002-08-17 09:36:01 +000052 * This structure is used to address each window in the PCMCIA controller.
53 *
54 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
55 * after pcmcia_win_t[n]...
56 */
57
58typedef struct {
59 ulong br;
60 ulong or;
61} pcmcia_win_t;
62
63/*
64 * Definitions for PCMCIA control registers to operate in IDE mode
65 *
66 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
67 * to be done later (depending on CPU clock)
68 */
69
70/* Window 0:
71 * Base: 0xFE100000 CS1
72 * Port Size: 2 Bytes
73 * Port Size: 16 Bit
74 * Common Memory Space
75 */
76
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
78#define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
wdenkaffae2b2002-08-17 09:36:01 +000079 | PCMCIA_PPS_16 \
80 | PCMCIA_PRS_MEM \
81 | PCMCIA_SLOT_x \
82 | PCMCIA_PV \
83 )
84
85/* Window 1:
86 * Base: 0xFE100080 CS1
87 * Port Size: 8 Bytes
88 * Port Size: 8 Bit
89 * Common Memory Space
90 */
91
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
93#define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
wdenkaffae2b2002-08-17 09:36:01 +000094 | PCMCIA_PPS_8 \
95 | PCMCIA_PRS_MEM \
96 | PCMCIA_SLOT_x \
97 | PCMCIA_PV \
98 )
99
100/* Window 2:
101 * Base: 0xFE100100 CS2
102 * Port Size: 8 Bytes
103 * Port Size: 8 Bit
104 * Common Memory Space
105 */
106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
108#define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
wdenkaffae2b2002-08-17 09:36:01 +0000109 | PCMCIA_PPS_8 \
110 | PCMCIA_PRS_MEM \
111 | PCMCIA_SLOT_x \
112 | PCMCIA_PV \
113 )
114
115/* Window 3:
116 * not used
117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_PCMCIA_PBR3 0
119#define CONFIG_SYS_PCMCIA_POR3 0
wdenkaffae2b2002-08-17 09:36:01 +0000120
121/* Window 4:
122 * Base: 0xFE100C00 CS1
123 * Port Size: 2 Bytes
124 * Port Size: 16 Bit
125 * Common Memory Space
126 */
127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
129#define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
wdenkaffae2b2002-08-17 09:36:01 +0000130 | PCMCIA_PPS_16 \
131 | PCMCIA_PRS_MEM \
132 | PCMCIA_SLOT_x \
133 | PCMCIA_PV \
134 )
135
136/* Window 5:
137 * Base: 0xFE100C80 CS1
138 * Port Size: 8 Bytes
139 * Port Size: 8 Bit
140 * Common Memory Space
141 */
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
144#define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
wdenkaffae2b2002-08-17 09:36:01 +0000145 | PCMCIA_PPS_8 \
146 | PCMCIA_PRS_MEM \
147 | PCMCIA_SLOT_x \
148 | PCMCIA_PV \
149 )
150
151/* Window 6:
152 * Base: 0xFE100D00 CS2
153 * Port Size: 8 Bytes
154 * Port Size: 8 Bit
155 * Common Memory Space
156 */
157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
159#define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
wdenkaffae2b2002-08-17 09:36:01 +0000160 | PCMCIA_PPS_8 \
161 | PCMCIA_PRS_MEM \
162 | PCMCIA_SLOT_x \
163 | PCMCIA_PV \
164 )
165
166/* Window 7:
167 * not used
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_PCMCIA_PBR7 0
170#define CONFIG_SYS_PCMCIA_POR7 0
wdenkaffae2b2002-08-17 09:36:01 +0000171
172/**********************************************************************/
173
174/*
175 * CIS Tupel codes
176 */
177#define CISTPL_NULL 0x00
178#define CISTPL_DEVICE 0x01
179#define CISTPL_LONGLINK_CB 0x02
180#define CISTPL_INDIRECT 0x03
181#define CISTPL_CONFIG_CB 0x04
182#define CISTPL_CFTABLE_ENTRY_CB 0x05
183#define CISTPL_LONGLINK_MFC 0x06
184#define CISTPL_BAR 0x07
185#define CISTPL_PWR_MGMNT 0x08
186#define CISTPL_EXTDEVICE 0x09
187#define CISTPL_CHECKSUM 0x10
188#define CISTPL_LONGLINK_A 0x11
189#define CISTPL_LONGLINK_C 0x12
190#define CISTPL_LINKTARGET 0x13
191#define CISTPL_NO_LINK 0x14
192#define CISTPL_VERS_1 0x15
193#define CISTPL_ALTSTR 0x16
194#define CISTPL_DEVICE_A 0x17
195#define CISTPL_JEDEC_C 0x18
196#define CISTPL_JEDEC_A 0x19
197#define CISTPL_CONFIG 0x1a
198#define CISTPL_CFTABLE_ENTRY 0x1b
199#define CISTPL_DEVICE_OC 0x1c
200#define CISTPL_DEVICE_OA 0x1d
201#define CISTPL_DEVICE_GEO 0x1e
202#define CISTPL_DEVICE_GEO_A 0x1f
203#define CISTPL_MANFID 0x20
204#define CISTPL_FUNCID 0x21
205#define CISTPL_FUNCE 0x22
206#define CISTPL_SWIL 0x23
207#define CISTPL_END 0xff
208
209/*
210 * CIS Function ID codes
211 */
212#define CISTPL_FUNCID_MULTI 0x00
213#define CISTPL_FUNCID_MEMORY 0x01
214#define CISTPL_FUNCID_SERIAL 0x02
215#define CISTPL_FUNCID_PARALLEL 0x03
216#define CISTPL_FUNCID_FIXED 0x04
217#define CISTPL_FUNCID_VIDEO 0x05
218#define CISTPL_FUNCID_NETWORK 0x06
219#define CISTPL_FUNCID_AIMS 0x07
220#define CISTPL_FUNCID_SCSI 0x08
221
222/*
223 * Fixed Disk FUNCE codes
224 */
225#define CISTPL_IDE_INTERFACE 0x01
226
227#define CISTPL_FUNCE_IDE_IFACE 0x01
228#define CISTPL_FUNCE_IDE_MASTER 0x02
229#define CISTPL_FUNCE_IDE_SLAVE 0x03
230
231/* First feature byte */
232#define CISTPL_IDE_SILICON 0x04
233#define CISTPL_IDE_UNIQUE 0x08
234#define CISTPL_IDE_DUAL 0x10
235
236/* Second feature byte */
237#define CISTPL_IDE_HAS_SLEEP 0x01
238#define CISTPL_IDE_HAS_STANDBY 0x02
239#define CISTPL_IDE_HAS_IDLE 0x04
240#define CISTPL_IDE_LOW_POWER 0x08
241#define CISTPL_IDE_REG_INHIBIT 0x10
242#define CISTPL_IDE_HAS_INDEX 0x20
243#define CISTPL_IDE_IOIS16 0x40
244
Jon Loeliger068b60a2007-07-10 10:27:39 -0500245#endif
wdenkaffae2b2002-08-17 09:36:01 +0000246
wdenkaffae2b2002-08-17 09:36:01 +0000247#endif /* _PCMCIA_H */