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Andy Fleming5f184712011-04-08 02:10:27 -05001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
Andy Flemingb21f87a32014-07-25 17:39:08 -05003 * Andy Fleming <afleming@gmail.com>
Andy Fleming5f184712011-04-08 02:10:27 -05004 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming5f184712011-04-08 02:10:27 -05006 *
7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
8 */
9
10#ifndef _PHY_H
11#define _PHY_H
12
13#include <linux/list.h>
14#include <linux/mii.h>
15#include <linux/ethtool.h>
16#include <linux/mdio.h>
17
Hannes Schmelzerdb40c1a2017-03-23 15:11:43 +010018#define PHY_FIXED_ID 0xa5a55a5a
19
Andy Fleming5f184712011-04-08 02:10:27 -050020#define PHY_MAX_ADDR 32
21
Shaohui Xieddcd1f32016-01-28 15:55:46 +080022#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
23
Florian Fainelli4dae6102016-01-13 16:59:33 +030024#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \
Andy Fleming5f184712011-04-08 02:10:27 -050025 SUPPORTED_TP | \
26 SUPPORTED_MII)
27
Florian Fainelli4dae6102016-01-13 16:59:33 +030028#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \
29 SUPPORTED_10baseT_Full)
30
31#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \
32 SUPPORTED_100baseT_Full)
33
34#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \
Andy Fleming5f184712011-04-08 02:10:27 -050035 SUPPORTED_1000baseT_Full)
36
Florian Fainelli4dae6102016-01-13 16:59:33 +030037#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \
38 PHY_100BT_FEATURES | \
39 PHY_DEFAULT_FEATURES)
40
41#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
42 PHY_1000BT_FEATURES)
43
Andy Fleming5f184712011-04-08 02:10:27 -050044#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
45 SUPPORTED_10000baseT_Full)
46
Stefan Roese4fb3f0c2014-10-22 12:13:15 +020047#ifndef PHY_ANEG_TIMEOUT
Andy Fleming5f184712011-04-08 02:10:27 -050048#define PHY_ANEG_TIMEOUT 4000
Stefan Roese4fb3f0c2014-10-22 12:13:15 +020049#endif
Andy Fleming5f184712011-04-08 02:10:27 -050050
51
52typedef enum {
53 PHY_INTERFACE_MODE_MII,
54 PHY_INTERFACE_MODE_GMII,
55 PHY_INTERFACE_MODE_SGMII,
Shengzhou Liuc35f8692014-10-23 17:20:57 +080056 PHY_INTERFACE_MODE_SGMII_2500,
Shaohui Xie7794b1a2013-03-25 07:39:31 +000057 PHY_INTERFACE_MODE_QSGMII,
Andy Fleming5f184712011-04-08 02:10:27 -050058 PHY_INTERFACE_MODE_TBI,
59 PHY_INTERFACE_MODE_RMII,
60 PHY_INTERFACE_MODE_RGMII,
61 PHY_INTERFACE_MODE_RGMII_ID,
62 PHY_INTERFACE_MODE_RGMII_RXID,
63 PHY_INTERFACE_MODE_RGMII_TXID,
64 PHY_INTERFACE_MODE_RTBI,
65 PHY_INTERFACE_MODE_XGMII,
Stefan Roesed11e9342017-02-23 11:58:26 +010066 PHY_INTERFACE_MODE_XAUI,
67 PHY_INTERFACE_MODE_RXAUI,
68 PHY_INTERFACE_MODE_SFI,
Simon Glassc74c8e62015-04-05 16:07:39 -060069 PHY_INTERFACE_MODE_NONE, /* Must be last */
70
71 PHY_INTERFACE_MODE_COUNT,
Andy Fleming5f184712011-04-08 02:10:27 -050072} phy_interface_t;
73
74static const char *phy_interface_strings[] = {
75 [PHY_INTERFACE_MODE_MII] = "mii",
76 [PHY_INTERFACE_MODE_GMII] = "gmii",
77 [PHY_INTERFACE_MODE_SGMII] = "sgmii",
Shengzhou Liuc35f8692014-10-23 17:20:57 +080078 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
Shaohui Xie7794b1a2013-03-25 07:39:31 +000079 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
Andy Fleming5f184712011-04-08 02:10:27 -050080 [PHY_INTERFACE_MODE_TBI] = "tbi",
81 [PHY_INTERFACE_MODE_RMII] = "rmii",
82 [PHY_INTERFACE_MODE_RGMII] = "rgmii",
83 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
84 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
85 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
86 [PHY_INTERFACE_MODE_RTBI] = "rtbi",
87 [PHY_INTERFACE_MODE_XGMII] = "xgmii",
Stefan Roesed11e9342017-02-23 11:58:26 +010088 [PHY_INTERFACE_MODE_XAUI] = "xaui",
89 [PHY_INTERFACE_MODE_RXAUI] = "rxaui",
90 [PHY_INTERFACE_MODE_SFI] = "sfi",
Andy Fleming5f184712011-04-08 02:10:27 -050091 [PHY_INTERFACE_MODE_NONE] = "",
92};
93
94static inline const char *phy_string_for_interface(phy_interface_t i)
95{
96 /* Default to unknown */
97 if (i > PHY_INTERFACE_MODE_NONE)
98 i = PHY_INTERFACE_MODE_NONE;
99
100 return phy_interface_strings[i];
101}
102
103
104struct phy_device;
105
106#define MDIO_NAME_LEN 32
107
108struct mii_dev {
109 struct list_head link;
110 char name[MDIO_NAME_LEN];
111 void *priv;
112 int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
113 int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
114 u16 val);
115 int (*reset)(struct mii_dev *bus);
116 struct phy_device *phymap[PHY_MAX_ADDR];
117 u32 phy_mask;
118};
119
120/* struct phy_driver: a structure which defines PHY behavior
121 *
122 * uid will contain a number which represents the PHY. During
123 * startup, the driver will poll the PHY to find out what its
124 * UID--as defined by registers 2 and 3--is. The 32-bit result
125 * gotten from the PHY will be masked to
126 * discard any bits which may change based on revision numbers
127 * unimportant to functionality
128 *
129 */
130struct phy_driver {
131 char *name;
132 unsigned int uid;
133 unsigned int mask;
134 unsigned int mmds;
135
136 u32 features;
137
138 /* Called to do any driver startup necessities */
139 /* Will be called during phy_connect */
140 int (*probe)(struct phy_device *phydev);
141
142 /* Called to configure the PHY, and modify the controller
143 * based on the results. Should be called after phy_connect */
144 int (*config)(struct phy_device *phydev);
145
146 /* Called when starting up the controller */
147 int (*startup)(struct phy_device *phydev);
148
149 /* Called when bringing down the controller */
150 int (*shutdown)(struct phy_device *phydev);
151
Stefano Babicb71841b2013-09-02 15:42:30 +0200152 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
153 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
154 u16 val);
Andy Fleming5f184712011-04-08 02:10:27 -0500155 struct list_head list;
156};
157
158struct phy_device {
159 /* Information about the PHY type */
160 /* And management functions */
161 struct mii_dev *bus;
162 struct phy_driver *drv;
163 void *priv;
164
Simon Glassc74c8e62015-04-05 16:07:39 -0600165#ifdef CONFIG_DM_ETH
166 struct udevice *dev;
167#else
Andy Fleming5f184712011-04-08 02:10:27 -0500168 struct eth_device *dev;
Simon Glassc74c8e62015-04-05 16:07:39 -0600169#endif
Andy Fleming5f184712011-04-08 02:10:27 -0500170
171 /* forced speed & duplex (no autoneg)
172 * partner speed & duplex & pause (autoneg)
173 */
174 int speed;
175 int duplex;
176
177 /* The most recently read link state */
178 int link;
179 int port;
180 phy_interface_t interface;
181
182 u32 advertising;
183 u32 supported;
184 u32 mmds;
185
186 int autoneg;
187 int addr;
188 int pause;
189 int asym_pause;
190 u32 phy_id;
191 u32 flags;
192};
193
Shaohui Xief55a7762013-11-14 19:00:31 +0800194struct fixed_link {
195 int phy_id;
196 int duplex;
197 int link_speed;
198 int pause;
199 int asym_pause;
200};
201
Andy Fleming5f184712011-04-08 02:10:27 -0500202static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
203{
204 struct mii_dev *bus = phydev->bus;
205
206 return bus->read(bus, phydev->addr, devad, regnum);
207}
208
209static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
210 u16 val)
211{
212 struct mii_dev *bus = phydev->bus;
213
214 return bus->write(bus, phydev->addr, devad, regnum, val);
215}
216
217#ifdef CONFIG_PHYLIB_10G
218extern struct phy_driver gen10g_driver;
219
220/* For now, XGMII is the only 10G interface */
221static inline int is_10g_interface(phy_interface_t interface)
222{
223 return interface == PHY_INTERFACE_MODE_XGMII;
224}
225
226#endif
227
228int phy_init(void);
229int phy_reset(struct phy_device *phydev);
Troy Kisky1adb4062012-10-22 16:40:43 +0000230struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
231 phy_interface_t interface);
Simon Glassc74c8e62015-04-05 16:07:39 -0600232#ifdef CONFIG_DM_ETH
233void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
234struct phy_device *phy_connect(struct mii_dev *bus, int addr,
235 struct udevice *dev,
236 phy_interface_t interface);
237#else
Troy Kisky1adb4062012-10-22 16:40:43 +0000238void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
Andy Fleming5f184712011-04-08 02:10:27 -0500239struct phy_device *phy_connect(struct mii_dev *bus, int addr,
240 struct eth_device *dev,
241 phy_interface_t interface);
Simon Glassc74c8e62015-04-05 16:07:39 -0600242#endif
Andy Fleming5f184712011-04-08 02:10:27 -0500243int phy_startup(struct phy_device *phydev);
244int phy_config(struct phy_device *phydev);
245int phy_shutdown(struct phy_device *phydev);
246int phy_register(struct phy_driver *drv);
Alexey Brodkinb18acb02016-01-13 16:59:34 +0300247int phy_set_supported(struct phy_device *phydev, u32 max_speed);
Andy Fleming5f184712011-04-08 02:10:27 -0500248int genphy_config_aneg(struct phy_device *phydev);
Troy Kisky8682aba2012-02-07 14:08:48 +0000249int genphy_restart_aneg(struct phy_device *phydev);
Andy Fleming5f184712011-04-08 02:10:27 -0500250int genphy_update_link(struct phy_device *phydev);
Yegor Yefremove2043f52012-11-28 11:15:17 +0100251int genphy_parse_link(struct phy_device *phydev);
Andy Fleming5f184712011-04-08 02:10:27 -0500252int genphy_config(struct phy_device *phydev);
253int genphy_startup(struct phy_device *phydev);
254int genphy_shutdown(struct phy_device *phydev);
255int gen10g_config(struct phy_device *phydev);
256int gen10g_startup(struct phy_device *phydev);
257int gen10g_shutdown(struct phy_device *phydev);
258int gen10g_discover_mmds(struct phy_device *phydev);
259
Kevin Smith24ae3962016-03-31 19:33:12 +0000260int phy_mv88e61xx_init(void);
Shaohui Xief7c38cf2014-12-30 18:32:04 +0800261int phy_aquantia_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500262int phy_atheros_init(void);
263int phy_broadcom_init(void);
Shengzhou Liu9b18e512014-11-10 18:32:29 +0800264int phy_cortina_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500265int phy_davicom_init(void);
Matt Porterf485c8a2013-03-20 05:38:13 +0000266int phy_et1011c_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500267int phy_lxt_init(void);
268int phy_marvell_init(void);
269int phy_micrel_init(void);
270int phy_natsemi_init(void);
271int phy_realtek_init(void);
Vladimir Zapolskiyb6abf552011-12-29 15:18:37 +0000272int phy_smsc_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500273int phy_teranetics_init(void);
Edgar E. Iglesias721aed72015-09-25 23:46:08 -0700274int phy_ti_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500275int phy_vitesse_init(void);
Siva Durga Prasad Paladugued6fad32016-02-05 13:22:10 +0530276int phy_xilinx_init(void);
John Haechtena5fd13a2016-12-09 22:15:17 +0000277int phy_mscc_init(void);
Hannes Schmelzerdb40c1a2017-03-23 15:11:43 +0100278int phy_fixed_init(void);
Timur Tabia8366262011-10-18 18:44:34 -0500279
Fabio Estevam2fb63962014-02-15 14:52:00 -0200280int board_phy_config(struct phy_device *phydev);
Shengzhou Liu5707d5f2015-04-07 18:46:32 +0800281int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
Fabio Estevam2fb63962014-02-15 14:52:00 -0200282
Simon Glassc74c8e62015-04-05 16:07:39 -0600283/**
284 * phy_get_interface_by_name() - Look up a PHY interface name
285 *
286 * @str: PHY interface name, e.g. "mii"
287 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
288 */
289int phy_get_interface_by_name(const char *str);
290
Dan Murphy3ab72fe2016-05-02 15:46:00 -0500291/**
292 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
293 * is RGMII (all variants)
294 * @phydev: the phy_device struct
295 */
296static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
297{
298 return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
299 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
300}
301
Dan Murphy3c221af2016-05-02 15:46:01 -0500302/**
303 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
304 * is SGMII (all variants)
305 * @phydev: the phy_device struct
306 */
307static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
308{
309 return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
310 phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
311}
312
Timur Tabia8366262011-10-18 18:44:34 -0500313/* PHY UIDs for various PHYs that are referenced in external code */
Shengzhou Liu9b18e512014-11-10 18:32:29 +0800314#define PHY_UID_CS4340 0x13e51002
Timur Tabia8366262011-10-18 18:44:34 -0500315#define PHY_UID_TN2020 0x00a19410
316
Andy Fleming5f184712011-04-08 02:10:27 -0500317#endif