Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Allwinner A80 APB0 Bus Clock |
| 8 | |
| 9 | maintainers: |
| 10 | - Chen-Yu Tsai <wens@csie.org> |
| 11 | - Maxime Ripard <mripard@kernel.org> |
| 12 | |
| 13 | deprecated: true |
| 14 | |
| 15 | properties: |
| 16 | "#clock-cells": |
| 17 | const: 0 |
| 18 | |
| 19 | compatible: |
| 20 | enum: |
| 21 | - allwinner,sun9i-a80-apb0-clk |
| 22 | - allwinner,sun9i-a80-apb1-clk |
| 23 | |
| 24 | reg: |
| 25 | maxItems: 1 |
| 26 | |
| 27 | clocks: |
| 28 | maxItems: 2 |
| 29 | description: > |
| 30 | The parent order must match the hardware programming order. |
| 31 | |
| 32 | clock-output-names: |
| 33 | maxItems: 1 |
| 34 | |
| 35 | required: |
| 36 | - "#clock-cells" |
| 37 | - compatible |
| 38 | - reg |
| 39 | - clocks |
| 40 | - clock-output-names |
| 41 | |
| 42 | additionalProperties: false |
| 43 | |
| 44 | examples: |
| 45 | - | |
| 46 | clk@6000070 { |
| 47 | #clock-cells = <0>; |
| 48 | compatible = "allwinner,sun9i-a80-apb0-clk"; |
| 49 | reg = <0x06000070 0x4>; |
| 50 | clocks = <&osc24M>, <&pll4>; |
| 51 | clock-output-names = "apb0"; |
| 52 | }; |
| 53 | |
| 54 | - | |
| 55 | clk@6000074 { |
| 56 | #clock-cells = <0>; |
| 57 | compatible = "allwinner,sun9i-a80-apb1-clk"; |
| 58 | reg = <0x06000074 0x4>; |
| 59 | clocks = <&osc24M>, <&pll4>; |
| 60 | clock-output-names = "apb1"; |
| 61 | }; |
| 62 | |
| 63 | ... |