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wdenk1eaeb582004-06-08 00:22:43 +00001/*
2 * Board specific setup info
3 *
4 * (C) Copyright 2003
5 * Texas Instruments, <www.ti.com>
6 * Kshitij Gupta <Kshitij@ti.com>
7 *
8 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
9 *
10 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <config.h>
31#include <version.h>
32
33#if defined(CONFIG_OMAP1610)
34#include <./configs/omap1510.h>
35#endif
36
37
38_TEXT_BASE:
39 .word TEXT_BASE /* sdram load addr from config.mk */
40
Wolfgang Denk87cb6862005-10-06 17:08:18 +020041.globl lowlevel_init
42lowlevel_init:
wdenk1eaeb582004-06-08 00:22:43 +000043
Stefan Roese6080a0e2006-05-10 10:55:16 +020044 /*------------------------------------------------------*
45 * Ensure i-cache is enabled *
46 * To configure TC regs without fetching instruction *
47 *------------------------------------------------------*/
48 mrc p15, 0, r0, c1, c0
49 orr r0, r0, #0x1000
50 mcr p15, 0, r0, c1, c0
wdenk1eaeb582004-06-08 00:22:43 +000051
52 /*------------------------------------------------------*
53 *mask all IRQs by setting all bits in the INTMR default*
54 *------------------------------------------------------*/
55 mov r1, #0xffffffff
56 ldr r0, =REG_IHL1_MIR
57 str r1, [r0]
58 ldr r0, =REG_IHL2_MIR
59 str r1, [r0]
60
61 /*------------------------------------------------------*
62 * Set up ARM CLM registers (IDLECT1) *
63 *------------------------------------------------------*/
64 ldr r0, REG_ARM_IDLECT1
65 ldr r1, VAL_ARM_IDLECT1
66 str r1, [r0]
67
68 /*------------------------------------------------------*
Stefan Roese6080a0e2006-05-10 10:55:16 +020069 * Set up ARM CLM registers (IDLECT2) *
wdenk1eaeb582004-06-08 00:22:43 +000070 *------------------------------------------------------*/
71 ldr r0, REG_ARM_IDLECT2
72 ldr r1, VAL_ARM_IDLECT2
73 str r1, [r0]
74
75 /*------------------------------------------------------*
Stefan Roese6080a0e2006-05-10 10:55:16 +020076 * Set up ARM CLM registers (IDLECT3) *
wdenk1eaeb582004-06-08 00:22:43 +000077 *------------------------------------------------------*/
78 ldr r0, REG_ARM_IDLECT3
79 ldr r1, VAL_ARM_IDLECT3
80 str r1, [r0]
81
Stefan Roese6080a0e2006-05-10 10:55:16 +020082 mov r1, #0x01 /* PER_EN bit */
wdenk1eaeb582004-06-08 00:22:43 +000083 ldr r0, REG_ARM_RSTCT2
Stefan Roese6080a0e2006-05-10 10:55:16 +020084 strh r1, [r0] /* CLKM; Peripheral reset. */
wdenk1eaeb582004-06-08 00:22:43 +000085
Stefan Roese6080a0e2006-05-10 10:55:16 +020086 /* Set CLKM to Sync-Scalable */
87 mov r1, #0x1000
wdenk1eaeb582004-06-08 00:22:43 +000088 ldr r0, REG_ARM_SYSST
Stefan Roese6080a0e2006-05-10 10:55:16 +020089
90 mov r2, #0
911: cmp r2, #1
92 streqh r1, [r0]
93 add r2, r2, #1
94 cmp r2, #0x100 /* wait for any bubbles to finish */
wdenk1eaeb582004-06-08 00:22:43 +000095 bne 1b
Stefan Roese6080a0e2006-05-10 10:55:16 +020096
wdenk1eaeb582004-06-08 00:22:43 +000097 ldr r1, VAL_ARM_CKCTL
98 ldr r0, REG_ARM_CKCTL
99 strh r1, [r0]
100
101 /* a few nops to let settle */
102 nop
103 nop
104 nop
105 nop
106 nop
107 nop
108 nop
109 nop
110 nop
111 nop
112
113 /* setup DPLL 1 */
114 /* Ramp up the clock to 96Mhz */
115 ldr r1, VAL_DPLL1_CTL
116 ldr r0, REG_DPLL1_CTL
117 strh r1, [r0]
Stefan Roese6080a0e2006-05-10 10:55:16 +0200118 ands r1, r1, #0x10 /* Check if PLL is enabled. */
119 beq lock_end /* Do not look for lock if BYPASS selected */
wdenk1eaeb582004-06-08 00:22:43 +00001202:
121 ldrh r1, [r0]
Stefan Roese6080a0e2006-05-10 10:55:16 +0200122 ands r1, r1, #0x01 /* Check the LOCK bit.*/
123 beq 2b /* loop until bit goes hi. */
wdenk1eaeb582004-06-08 00:22:43 +0000124lock_end:
125
wdenk1eaeb582004-06-08 00:22:43 +0000126 /*------------------------------------------------------*
Stefan Roese6080a0e2006-05-10 10:55:16 +0200127 * Turn off the watchdog during init... *
wdenk1eaeb582004-06-08 00:22:43 +0000128 *------------------------------------------------------*/
129 ldr r0, REG_WATCHDOG
130 ldr r1, WATCHDOG_VAL1
131 str r1, [r0]
132 ldr r1, WATCHDOG_VAL2
133 str r1, [r0]
134 ldr r0, REG_WSPRDOG
135 ldr r1, WSPRDOG_VAL1
136 str r1, [r0]
137 ldr r0, REG_WWPSDOG
138
139watch1Wait:
140 ldr r1, [r0]
141 tst r1, #0x10
142 bne watch1Wait
143
144 ldr r0, REG_WSPRDOG
145 ldr r1, WSPRDOG_VAL2
146 str r1, [r0]
147 ldr r0, REG_WWPSDOG
148watch2Wait:
149 ldr r1, [r0]
150 tst r1, #0x10
151 bne watch2Wait
152
wdenk1eaeb582004-06-08 00:22:43 +0000153 /* Set memory timings corresponding to the new clock speed */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200154 ldr r3, VAL_SDRAM_CONFIG_SDF0
wdenk1eaeb582004-06-08 00:22:43 +0000155
156 /* Check execution location to determine current execution location
157 * and branch to appropriate initialization code.
158 */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200159 mov r0, #0x10000000 /* Load physical SDRAM base. */
160 mov r1, pc /* Get current execution location. */
161 cmp r1, r0 /* Compare. */
162 bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
163
164 /* identify the device revision, -- TMX or TMP(TMS) */
165 ldr r0, REG_DEVICE_ID
166 ldr r1, [r0]
167
168 ldr r0, VAL_DEVICE_ID_TMP
169 mov r1, r1, lsl #15
170 mov r1, r1, lsr #16
171 cmp r0, r1
172 bne skip_TMP_Patch
173
174 /* Enable TMP/TMS device new features */
175 mov r0, #1
176 ldr r1, REG_TC_EMIFF_DOUBLER
177 str r0, [r1]
178
179 /* Enable new ac parameters */
180 mov r0, #0x0b
181 ldr r1, REG_SDRAM_CONFIG2
182 str r0, [r1]
183
184 ldr r3, VAL_SDRAM_CONFIG_SDF1
185
186skip_TMP_Patch:
wdenk1eaeb582004-06-08 00:22:43 +0000187
188 /*
189 * Delay for SDRAM initialization.
190 */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200191 mov r0, #0x1800 /* value should be checked */
wdenk1eaeb582004-06-08 00:22:43 +00001923:
Stefan Roese6080a0e2006-05-10 10:55:16 +0200193 subs r0, r0, #0x1 /* Decrement count */
wdenk1eaeb582004-06-08 00:22:43 +0000194 bne 3b
195
wdenk1eaeb582004-06-08 00:22:43 +0000196 /*
197 * Set SDRAM control values. Disable refresh before MRS command.
198 */
199
200 /* mobile ddr operation */
201 ldr r0, REG_SDRAM_OPERATION
202 mov r2, #07
203 str r2, [r0]
204
205 /* config register */
206 ldr r0, REG_SDRAM_CONFIG
Stefan Roese6080a0e2006-05-10 10:55:16 +0200207 str r3, [r0]
wdenk1eaeb582004-06-08 00:22:43 +0000208
209 /* manual command register */
210 ldr r0, REG_SDRAM_MANUAL_CMD
Stefan Roese6080a0e2006-05-10 10:55:16 +0200211
wdenk1eaeb582004-06-08 00:22:43 +0000212 /* issue set cke high */
213 mov r1, #CMD_SDRAM_CKE_SET_HIGH
214 str r1, [r0]
Stefan Roese6080a0e2006-05-10 10:55:16 +0200215
wdenk1eaeb582004-06-08 00:22:43 +0000216 /* issue nop */
217 mov r1, #CMD_SDRAM_NOP
218 str r1, [r0]
219
220 mov r2, #0x0100
221waitMDDR1:
222 subs r2, r2, #1
223 bne waitMDDR1 /* delay loop */
224
225 /* issue precharge */
226 mov r1, #CMD_SDRAM_PRECHARGE
227 str r1, [r0]
228
229 /* issue autorefresh x 2 */
230 mov r1, #CMD_SDRAM_AUTOREFRESH
231 str r1, [r0]
232 str r1, [r0]
233
234 /* mrs register ddr mobile */
235 ldr r0, REG_SDRAM_MRS
236 mov r1, #0x33
237 str r1, [r0]
238
239 /* emrs1 low-power register */
240 ldr r0, REG_SDRAM_EMRS1
241 /* self refresh on all banks */
242 mov r1, #0
243 str r1, [r0]
244
245 ldr r0, REG_DLL_URD_CONTROL
246 ldr r1, DLL_URD_CONTROL_VAL
247 str r1, [r0]
248
249 ldr r0, REG_DLL_LRD_CONTROL
250 ldr r1, DLL_LRD_CONTROL_VAL
251 str r1, [r0]
252
253 ldr r0, REG_DLL_WRT_CONTROL
254 ldr r1, DLL_WRT_CONTROL_VAL
255 str r1, [r0]
256
257 /* delay loop */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200258 mov r0, #0x0100
wdenk1eaeb582004-06-08 00:22:43 +0000259waitMDDR2:
Stefan Roese6080a0e2006-05-10 10:55:16 +0200260 subs r0, r0, #1
wdenk1eaeb582004-06-08 00:22:43 +0000261 bne waitMDDR2
262
263 /*
264 * Delay for SDRAM initialization.
265 */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200266 mov r0, #0x1800
wdenk1eaeb582004-06-08 00:22:43 +00002674:
Stefan Roese6080a0e2006-05-10 10:55:16 +0200268 subs r0, r0, #1 /* Decrement count. */
wdenk1eaeb582004-06-08 00:22:43 +0000269 bne 4b
270 b common_tc
271
272skip_sdram:
wdenk1eaeb582004-06-08 00:22:43 +0000273 ldr r0, REG_SDRAM_CONFIG
Stefan Roese6080a0e2006-05-10 10:55:16 +0200274 str r3, [r0]
wdenk1eaeb582004-06-08 00:22:43 +0000275
276common_tc:
277 /* slow interface */
278 ldr r1, VAL_TC_EMIFS_CS0_CONFIG
279 ldr r0, REG_TC_EMIFS_CS0_CONFIG
280 str r1, [r0] /* Chip Select 0 */
281
282 ldr r1, VAL_TC_EMIFS_CS1_CONFIG
283 ldr r0, REG_TC_EMIFS_CS1_CONFIG
284 str r1, [r0] /* Chip Select 1 */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200285
wdenk1eaeb582004-06-08 00:22:43 +0000286 ldr r1, VAL_TC_EMIFS_CS3_CONFIG
287 ldr r0, REG_TC_EMIFS_CS3_CONFIG
288 str r1, [r0] /* Chip Select 3 */
289
Stefan Roese6080a0e2006-05-10 10:55:16 +0200290 ldr r1, VAL_TC_EMIFS_DWS
291 ldr r0, REG_TC_EMIFS_DWS
292 str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */
293
wdenk1eaeb582004-06-08 00:22:43 +0000294#ifdef CONFIG_H2_OMAP1610
295 /* inserting additional 2 clock cycle hold time for LAN */
296 ldr r0, REG_TC_EMIFS_CS1_ADVANCED
297 ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
298 str r1, [r0]
299#endif
300 /* Start MPU Timer 1 */
301 ldr r0, REG_MPU_LOAD_TIMER
302 ldr r1, VAL_MPU_LOAD_TIMER
303 str r1, [r0]
304
305 ldr r0, REG_MPU_CNTL_TIMER
306 ldr r1, VAL_MPU_CNTL_TIMER
307 str r1, [r0]
308
309 /* back to arch calling code */
310 mov pc, lr
311
312 /* the literal pools origin */
313 .ltorg
314
Stefan Roese6080a0e2006-05-10 10:55:16 +0200315REG_DEVICE_ID: /* 32 bits */
316 .word 0xfffe2004
317REG_TC_EMIFS_CONFIG:
wdenk1eaeb582004-06-08 00:22:43 +0000318 .word 0xfffecc0c
319REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
320 .word 0xfffecc10
321REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
322 .word 0xfffecc14
323REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
324 .word 0xfffecc18
325REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
326 .word 0xfffecc1c
Stefan Roese6080a0e2006-05-10 10:55:16 +0200327REG_TC_EMIFS_DWS: /* 32 bits */
328 .word 0xfffecc40
wdenk1eaeb582004-06-08 00:22:43 +0000329#ifdef CONFIG_H2_OMAP1610
330REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
331 .word 0xfffecc54
332#endif
333
334/* MPU clock/reset/power mode control registers */
335REG_ARM_CKCTL: /* 16 bits */
336 .word 0xfffece00
wdenk1eaeb582004-06-08 00:22:43 +0000337REG_ARM_IDLECT3: /* 16 bits */
338 .word 0xfffece24
339REG_ARM_IDLECT2: /* 16 bits */
340 .word 0xfffece08
341REG_ARM_IDLECT1: /* 16 bits */
342 .word 0xfffece04
wdenk1eaeb582004-06-08 00:22:43 +0000343REG_ARM_RSTCT2: /* 16 bits */
344 .word 0xfffece14
345REG_ARM_SYSST: /* 16 bits */
346 .word 0xfffece18
Stefan Roese6080a0e2006-05-10 10:55:16 +0200347
wdenk1eaeb582004-06-08 00:22:43 +0000348/* DPLL control registers */
349REG_DPLL1_CTL: /* 16 bits */
350 .word 0xfffecf00
351
352/* Watch Dog register */
353/* secure watchdog stop */
354REG_WSPRDOG:
355 .word 0xfffeb048
356/* watchdog write pending */
357REG_WWPSDOG:
358 .word 0xfffeb034
359
360WSPRDOG_VAL1:
361 .word 0x0000aaaa
362WSPRDOG_VAL2:
363 .word 0x00005555
364
365/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
366 counter @8192 rows, 10 ns, 8 burst */
367REG_SDRAM_CONFIG:
368 .word 0xfffecc20
Stefan Roese6080a0e2006-05-10 10:55:16 +0200369REG_SDRAM_CONFIG2:
370 .word 0xfffecc3c
371REG_TC_EMIFF_DOUBLER: /* 32 bits */
372 .word 0xfffecc60
wdenk1eaeb582004-06-08 00:22:43 +0000373
374/* Operation register */
375REG_SDRAM_OPERATION:
376 .word 0xfffecc80
377
378/* Manual command register */
379REG_SDRAM_MANUAL_CMD:
380 .word 0xfffecc84
381
382/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
383REG_SDRAM_MRS:
384 .word 0xfffecc70
385
386/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
387REG_SDRAM_EMRS1:
388 .word 0xfffecc78
389
390/* WRT DLL register */
391REG_DLL_WRT_CONTROL:
392 .word 0xfffecc68
393DLL_WRT_CONTROL_VAL:
Stefan Roese6080a0e2006-05-10 10:55:16 +0200394 .word 0x03f00002 /* Phase of 72deg, write offset +31 */
wdenk1eaeb582004-06-08 00:22:43 +0000395
396/* URD DLL register */
397REG_DLL_URD_CONTROL:
398 .word 0xfffeccc0
399DLL_URD_CONTROL_VAL:
Stefan Roese6080a0e2006-05-10 10:55:16 +0200400 .word 0x00800002 /* Phase of 72deg, read offset +31 */
wdenk1eaeb582004-06-08 00:22:43 +0000401
402/* LRD DLL register */
403REG_DLL_LRD_CONTROL:
404 .word 0xfffecccc
Stefan Roese6080a0e2006-05-10 10:55:16 +0200405DLL_LRD_CONTROL_VAL:
406 .word 0x00800002 /* read offset +31 */
wdenk1eaeb582004-06-08 00:22:43 +0000407
408REG_WATCHDOG:
409 .word 0xfffec808
Stefan Roese6080a0e2006-05-10 10:55:16 +0200410WATCHDOG_VAL1:
411 .word 0x000000f5
412WATCHDOG_VAL2:
413 .word 0x000000a0
wdenk1eaeb582004-06-08 00:22:43 +0000414
415REG_MPU_LOAD_TIMER:
Stefan Roese6080a0e2006-05-10 10:55:16 +0200416 .word 0xfffec504
wdenk1eaeb582004-06-08 00:22:43 +0000417REG_MPU_CNTL_TIMER:
418 .word 0xfffec500
Stefan Roese6080a0e2006-05-10 10:55:16 +0200419VAL_MPU_LOAD_TIMER:
420 .word 0xffffffff
421VAL_MPU_CNTL_TIMER:
422 .word 0xffffffa1
wdenk1eaeb582004-06-08 00:22:43 +0000423
424/* 96 MHz Samsung Mobile DDR */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200425/* Original setting for TMX device */
426VAL_SDRAM_CONFIG_SDF0:
427 .word 0x0014e6fe
wdenk1eaeb582004-06-08 00:22:43 +0000428
Stefan Roese6080a0e2006-05-10 10:55:16 +0200429/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
430VAL_SDRAM_CONFIG_SDF1:
431 .word 0x0114e6fe
wdenk1eaeb582004-06-08 00:22:43 +0000432
433VAL_ARM_CKCTL:
Stefan Roese6080a0e2006-05-10 10:55:16 +0200434 .word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */
wdenk1eaeb582004-06-08 00:22:43 +0000435VAL_DPLL1_CTL:
436 .word 0x2830
437
438#ifdef CONFIG_OSK_OMAP5912
439VAL_TC_EMIFS_CS0_CONFIG:
440 .word 0x002130b0
441VAL_TC_EMIFS_CS1_CONFIG:
Stefan Roesed1dd22f2006-05-10 11:49:37 +0200442 .word 0x00001133
wdenk1eaeb582004-06-08 00:22:43 +0000443VAL_TC_EMIFS_CS2_CONFIG:
444 .word 0x000055f0
445VAL_TC_EMIFS_CS3_CONFIG:
Stefan Roese6080a0e2006-05-10 10:55:16 +0200446 .word 0x88013141
447VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */
448 .word 0x000000c0
449VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */
450 .word 0xb65f
wdenk1eaeb582004-06-08 00:22:43 +0000451#endif
452
453#ifdef CONFIG_H2_OMAP1610
454VAL_TC_EMIFS_CS0_CONFIG:
455 .word 0x00203331
456VAL_TC_EMIFS_CS1_CONFIG:
457 .word 0x8180fff3
458VAL_TC_EMIFS_CS2_CONFIG:
459 .word 0xf800f22a
460VAL_TC_EMIFS_CS3_CONFIG:
Stefan Roese6080a0e2006-05-10 10:55:16 +0200461 .word 0x88013141
wdenk1eaeb582004-06-08 00:22:43 +0000462VAL_TC_EMIFS_CS1_ADVANCED:
463 .word 0x00000022
464#endif
465
wdenk1eaeb582004-06-08 00:22:43 +0000466VAL_ARM_IDLECT1:
467 .word 0x00000400
wdenk1eaeb582004-06-08 00:22:43 +0000468VAL_ARM_IDLECT2:
469 .word 0x00000886
470VAL_ARM_IDLECT3:
471 .word 0x00000015
472
wdenk1eaeb582004-06-08 00:22:43 +0000473/* command values */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200474.equ CMD_SDRAM_NOP, 0x00000000
475.equ CMD_SDRAM_PRECHARGE, 0x00000001
476.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
477.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007