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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Bo Shen3225f342013-05-12 22:40:54 +00002/*
3 * (C) Copyright 2010
4 * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
5 * (C) Copyright 2009
6 * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 * (C) Copyright 2013
8 * Bo Shen <voice.shen@atmel.com>
Bo Shen3225f342013-05-12 22:40:54 +00009 */
10
11#include <common.h>
Simon Glass9edefc22019-11-14 12:57:37 -070012#include <cpu_func.h>
Simon Glass691d7192020-05-10 11:40:02 -060013#include <init.h>
Simon Glass2189d5f2019-11-14 12:57:20 -070014#include <vsprintf.h>
Bo Shen3225f342013-05-12 22:40:54 +000015#include <asm/io.h>
16#include <asm/arch/hardware.h>
Bo Shen3225f342013-05-12 22:40:54 +000017#include <asm/arch/at91_pit.h>
18#include <asm/arch/at91_gpbr.h>
19#include <asm/arch/clk.h>
20
21#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
22#define CONFIG_SYS_AT91_MAIN_CLOCK 0
23#endif
24
25int arch_cpu_init(void)
26{
Nicolas Ferre62495e22020-11-11 13:15:08 +020027#if defined(CONFIG_CLK_CCF)
28 return 0;
29#else
Bo Shen3225f342013-05-12 22:40:54 +000030 return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
Nicolas Ferre62495e22020-11-11 13:15:08 +020031#endif
Bo Shen3225f342013-05-12 22:40:54 +000032}
33
34void arch_preboot_os(void)
35{
Eugen Hristev919c4f32020-08-20 16:11:52 +030036#if (IS_ENABLED(CONFIG_ATMEL_PIT_TIMER))
Bo Shen3225f342013-05-12 22:40:54 +000037 ulong cpiv;
38 at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
39
40 cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
41
42 /*
43 * Disable PITC
44 * Add 0x1000 to current counter to stop it faster
45 * without waiting for wrapping back to 0
46 */
47 writel(cpiv + 0x1000, &pit->mr);
Eugen Hristev919c4f32020-08-20 16:11:52 +030048#endif
Bo Shen3225f342013-05-12 22:40:54 +000049}
50
51#if defined(CONFIG_DISPLAY_CPUINFO)
52int print_cpuinfo(void)
53{
54 char buf[32];
55
56 printf("CPU: %s\n", get_cpu_name());
57 printf("Crystal frequency: %8s MHz\n",
58 strmhz(buf, get_main_clk_rate()));
59 printf("CPU clock : %8s MHz\n",
60 strmhz(buf, get_cpu_clk_rate()));
61 printf("Master clock : %8s MHz\n",
62 strmhz(buf, get_mck_clk_rate()));
63
64 return 0;
65}
66#endif
67
68void enable_caches(void)
69{
Wu, Joshd337a092014-05-19 19:51:28 +080070 icache_enable();
71 dcache_enable();
Bo Shen3225f342013-05-12 22:40:54 +000072}
73
Wenyou Yangce396802015-09-08 14:38:26 +080074#define ATMEL_CHIPID_CIDR_VERSION 0x1f
75
Bo Shen3225f342013-05-12 22:40:54 +000076unsigned int get_chip_id(void)
77{
Wenyou Yangce396802015-09-08 14:38:26 +080078 return readl(ATMEL_CHIPID_CIDR) & ~ATMEL_CHIPID_CIDR_VERSION;
Bo Shen3225f342013-05-12 22:40:54 +000079}
80
81unsigned int get_extension_chip_id(void)
82{
Wenyou Yangce396802015-09-08 14:38:26 +080083 return readl(ATMEL_CHIPID_EXID);
Bo Shen3225f342013-05-12 22:40:54 +000084}