| Chris Zankel | c978b52 | 2016-08-10 18:36:44 +0300 | [diff] [blame] | 1 | menu "Xtensa architecture" |
| 2 | depends on XTENSA |
| 3 | |
| 4 | config SYS_ARCH |
| 5 | string |
| 6 | default "xtensa" |
| 7 | |
| 8 | config SYS_CPU |
| 9 | string "Xtensa Core Variant" |
| 10 | |
| 11 | choice |
| 12 | prompt "Target select" |
| 13 | |
| Chris Zankel | 7e270ec | 2016-08-10 18:36:48 +0300 | [diff] [blame] | 14 | config TARGET_XTFPGA |
| 15 | bool "Support XTFPGA" |
| Chris Zankel | c978b52 | 2016-08-10 18:36:44 +0300 | [diff] [blame] | 16 | |
| 17 | endchoice |
| 18 | |
| Trevor Woerner | a0aba8a | 2019-05-03 09:40:59 -0400 | [diff] [blame] | 19 | config SYS_ICACHE_OFF |
| 20 | bool "Do not enable icache" |
| 21 | default n |
| 22 | help |
| 23 | Do not enable instruction cache in U-Boot. |
| 24 | |
| Trevor Woerner | 1001502 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 25 | config SPL_SYS_ICACHE_OFF |
| 26 | bool "Do not enable icache in SPL" |
| 27 | depends on SPL |
| 28 | default SYS_ICACHE_OFF |
| 29 | help |
| 30 | Do not enable instruction cache in SPL. |
| 31 | |
| Trevor Woerner | a0aba8a | 2019-05-03 09:40:59 -0400 | [diff] [blame] | 32 | config SYS_DCACHE_OFF |
| 33 | bool "Do not enable dcache" |
| 34 | default n |
| 35 | help |
| 36 | Do not enable data cache in U-Boot. |
| 37 | |
| Trevor Woerner | 1001502 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 38 | config SPL_SYS_DCACHE_OFF |
| 39 | bool "Do not enable dcache in SPL" |
| 40 | depends on SPL |
| 41 | default SYS_DCACHE_OFF |
| 42 | help |
| 43 | Do not enable data cache in SPL. |
| 44 | |
| Chris Zankel | 7e270ec | 2016-08-10 18:36:48 +0300 | [diff] [blame] | 45 | source "board/cadence/xtfpga/Kconfig" |
| Chris Zankel | c978b52 | 2016-08-10 18:36:44 +0300 | [diff] [blame] | 46 | |
| 47 | endmenu |