blob: 05ddeed2a64b4b196c29aa76e0c5bdae16703f5f [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peng Fan0cb3d822017-02-22 16:21:41 +08002/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
Peng Fan0cb3d822017-02-22 16:21:41 +08004 */
5#include <common.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06006#include <log.h>
Peng Fan0cb3d822017-02-22 16:21:41 +08007#include <asm/io.h>
8#include <asm/arch/imx-regs.h>
9#include <asm/arch/iomux.h>
10
11static void *base = (void *)IOMUXC_BASE_ADDR;
12
13/*
14 * iomuxc0 base address. In imx7ulp-pins.h,
15 * the offsets of pins in iomuxc0 are from 0xD000,
16 * so we set the base address to (0x4103D000 - 0xD000 = 0x41030000)
17 */
18static void *base_mports = (void *)(AIPS0_BASE + 0x30000);
19
20/*
21 * configures a single pad in the iomuxer
22 */
23void mx7ulp_iomux_setup_pad(iomux_cfg_t pad)
24{
25 u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
26 u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
27 u32 sel_input_ofs =
28 (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
29 u32 sel_input =
30 (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
31 u32 pad_ctrl_ofs = mux_ctrl_ofs;
32 u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
33
34 debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input = 0x%X(0x%X) pad_ctrl = 0x%X(0x%X)\r\n",
35 pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input,
36 pad_ctrl_ofs, pad_ctrl);
37
38 if (mux_mode & IOMUX_CONFIG_MPORTS) {
39 mux_mode &= ~IOMUX_CONFIG_MPORTS;
40 base = base_mports;
41 } else {
42 base = (void *)IOMUXC_BASE_ADDR;
43 }
44
45 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
46 IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs);
47
48 if (sel_input_ofs)
49 __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT),
50 base + sel_input_ofs);
51
52 if (!(pad_ctrl & NO_PAD_CTRL))
53 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
54 IOMUXC_PCR_MUX_ALT_MASK) |
55 (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)),
56 base + pad_ctrl_ofs);
57}
58
59/* configures a list of pads within declared with IOMUX_PADS macro */
60void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
61 unsigned count)
62{
63 iomux_cfg_t const *p = pad_list;
64 int i;
65
66 for (i = 0; i < count; i++) {
67 mx7ulp_iomux_setup_pad(*p);
68 p++;
69 }
70}