blob: 2c9ada060cff08139d1cca0a49203108cc525589 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass7e4154a2014-06-02 22:04:48 -06002/*
3 *
4 * Common functions for OMAP4/5 based boards
5 *
6 * (C) Copyright 2010
7 * Texas Instruments, <www.ti.com>
8 *
9 * Author :
10 * Aneesh V <aneesh@ti.com>
11 * Steve Sakoman <steve@sakoman.com>
Simon Glass7e4154a2014-06-02 22:04:48 -060012 */
13
14#include <common.h>
Simon Glass9edefc22019-11-14 12:57:37 -070015#include <cpu_func.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060016#include <log.h>
Simon Glass7e4154a2014-06-02 22:04:48 -060017#include <asm/cache.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
Keerthy859c70d2016-09-14 10:43:29 +053021/*
22 * Without LPAE short descriptors are used
23 * Set C - Cache Bit3
24 * Set B - Buffer Bit2
25 * The last 2 bits set to 0b10
26 * Do Not set XN bit4
27 * So value is 0xe
28 *
29 * With LPAE cache configuration happens via MAIR0 register
30 * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
31 * 0xFF maps to Cache writeback with Read and Write Allocate set
32 * The bits[1:0] should have the value 0b01 for the first level
33 * descriptor.
34 * So the value is 0xd
35 */
36
37#ifdef CONFIG_ARMV7_LPAE
38#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
39#else
40#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
41#endif
42
Simon Glass7e4154a2014-06-02 22:04:48 -060043#define ARMV7_DOMAIN_CLIENT 1
44#define ARMV7_DOMAIN_MASK (0x3 << 0)
45
46void enable_caches(void)
47{
Lokesh Vutla7ce85312018-05-03 20:34:49 +053048
49 /* Enable I cache if not enabled */
50 if (!icache_status())
51 icache_enable();
52
Simon Glass7e4154a2014-06-02 22:04:48 -060053 dcache_enable();
54}
55
56void dram_bank_mmu_setup(int bank)
57{
58 bd_t *bd = gd->bd;
59 int i;
60
Keerthyc268a9b2016-09-14 10:43:28 +053061 u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
62 u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
Simon Glass7e4154a2014-06-02 22:04:48 -060063 u32 end = start + size;
64
65 debug("%s: bank: %d\n", __func__, bank);
66 for (i = start; i < end; i++)
Keerthy859c70d2016-09-14 10:43:29 +053067 set_section_dcache(i, ARMV7_DCACHE_POLICY);
Simon Glass7e4154a2014-06-02 22:04:48 -060068}
69
70void arm_init_domains(void)
71{
72 u32 reg;
73
74 reg = get_dacr();
75 /*
76 * Set DOMAIN to client access so that all permissions
77 * set in pagetables are validated by the mmu.
78 */
79 reg &= ~ARMV7_DOMAIN_MASK;
80 reg |= ARMV7_DOMAIN_CLIENT;
81 set_dacr(reg);
82}