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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simeke6a9ed02015-11-20 13:17:22 +01002/*
3 * Copyright 2015 - 2016 Xilinx, Inc.
4 *
5 * Michal Simek <michal.simek@xilinx.com>
Michal Simeke6a9ed02015-11-20 13:17:22 +01006 */
7
8#include <common.h>
Simon Glass4d72caa2020-05-10 11:40:01 -06009#include <image.h>
Simon Glass52559322019-11-14 12:57:46 -070010#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Michal Simeke6a9ed02015-11-20 13:17:22 +010012#include <spl.h>
13
14#include <asm/io.h>
15#include <asm/spl.h>
16#include <asm/arch/hardware.h>
Michal Simeke82024d2019-12-03 15:02:50 +010017#include <asm/arch/psu_init_gpl.h>
Michal Simeke6a9ed02015-11-20 13:17:22 +010018#include <asm/arch/sys_proto.h>
19
20void board_init_f(ulong dummy)
21{
Michal Simek55de0922017-07-12 13:08:41 +020022 board_early_init_f();
Michal Simeke6a9ed02015-11-20 13:17:22 +010023 board_early_init_r();
Michal Simeke6a9ed02015-11-20 13:17:22 +010024}
25
Michal Simek48255f52016-08-15 09:41:36 +020026static void ps_mode_reset(ulong mode)
27{
Michal Simek48255f52016-08-15 09:41:36 +020028 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
29 &crlapb_base->boot_pin_ctrl);
30 udelay(5);
31 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
32 mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
33 &crlapb_base->boot_pin_ctrl);
34}
35
36/*
37 * Set default PS_MODE1 which is used for USB ULPI phy reset
38 * Also other resets can be connected to this certain pin
39 */
40#ifndef MODE_RESET
41# define MODE_RESET PS_MODE1
42#endif
43
Michal Simeke6a9ed02015-11-20 13:17:22 +010044#ifdef CONFIG_SPL_BOARD_INIT
45void spl_board_init(void)
46{
47 preloader_console_init();
Michal Simek48255f52016-08-15 09:41:36 +020048 ps_mode_reset(MODE_RESET);
Michal Simeke6a9ed02015-11-20 13:17:22 +010049 board_init();
Michal Simeke82024d2019-12-03 15:02:50 +010050 psu_post_config_data();
Michal Simeke6a9ed02015-11-20 13:17:22 +010051}
52#endif
53
Michal Simekde79ca952019-12-09 13:00:57 +010054void board_boot_order(u32 *spl_boot_list)
55{
56 spl_boot_list[0] = spl_boot_device();
57
58 if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
59 spl_boot_list[1] = BOOT_DEVICE_MMC2;
60 if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
61 spl_boot_list[1] = BOOT_DEVICE_MMC1;
Michal Simekf1433d02020-03-11 15:00:51 +010062
63 spl_boot_list[2] = BOOT_DEVICE_RAM;
Michal Simekde79ca952019-12-09 13:00:57 +010064}
65
Michal Simeke6a9ed02015-11-20 13:17:22 +010066u32 spl_boot_device(void)
67{
68 u32 reg = 0;
69 u8 bootmode;
70
Michal Simek7f491d72016-08-30 16:17:27 +020071#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
72 /* Change default boot mode at run-time */
Michal Simek47359a02016-10-25 11:43:02 +020073 writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
Michal Simek7f491d72016-08-30 16:17:27 +020074 &crlapb_base->boot_mode);
75#endif
76
Michal Simeke6a9ed02015-11-20 13:17:22 +010077 reg = readl(&crlapb_base->boot_mode);
Michal Simek47359a02016-10-25 11:43:02 +020078 if (reg >> BOOT_MODE_ALT_SHIFT)
79 reg >>= BOOT_MODE_ALT_SHIFT;
80
Michal Simeke6a9ed02015-11-20 13:17:22 +010081 bootmode = reg & BOOT_MODES_MASK;
82
83 switch (bootmode) {
84 case JTAG_MODE:
85 return BOOT_DEVICE_RAM;
86#ifdef CONFIG_SPL_MMC_SUPPORT
Michal Simeke6a9ed02015-11-20 13:17:22 +010087 case SD_MODE1:
Michal Simekb0259c82017-03-02 11:02:55 +010088 case SD1_LSHFT_MODE: /* not working on silicon v1 */
Jean-Francois Dagenaise3fdf5d2017-04-02 21:44:34 -040089 return BOOT_DEVICE_MMC2;
Jean-Francois Dagenaise3fdf5d2017-04-02 21:44:34 -040090 case SD_MODE:
91 case EMMC_MODE:
Michal Simeke6a9ed02015-11-20 13:17:22 +010092 return BOOT_DEVICE_MMC1;
93#endif
Andrew F. Davis6536ca42019-01-17 13:43:02 -060094#ifdef CONFIG_SPL_DFU
Michal Simekd58fc122016-08-19 14:14:52 +020095 case USB_MODE:
96 return BOOT_DEVICE_DFU;
97#endif
Michal Simek26610812016-10-26 09:24:32 +020098#ifdef CONFIG_SPL_SATA_SUPPORT
99 case SW_SATA_MODE:
100 return BOOT_DEVICE_SATA;
101#endif
Michal Simek40d1f8a2017-11-02 09:15:05 +0100102#ifdef CONFIG_SPL_SPI_SUPPORT
103 case QSPI_MODE_24BIT:
104 case QSPI_MODE_32BIT:
105 return BOOT_DEVICE_SPI;
106#endif
Michal Simeke6a9ed02015-11-20 13:17:22 +0100107 default:
108 printf("Invalid Boot Mode:0x%x\n", bootmode);
109 break;
110 }
111
112 return 0;
113}
114
Michal Simeke6a9ed02015-11-20 13:17:22 +0100115#ifdef CONFIG_SPL_OS_BOOT
116int spl_start_uboot(void)
117{
Michal Simeke6a9ed02015-11-20 13:17:22 +0100118 return 0;
119}
120#endif
121
122#ifdef CONFIG_SPL_LOAD_FIT
123int board_fit_config_name_match(const char *name)
124{
125 /* Just empty function now - can't decide what to choose */
126 debug("%s: %s\n", __func__, name);
127
Michal Simekb4f84682019-12-09 08:39:19 +0100128 return -1;
Michal Simeke6a9ed02015-11-20 13:17:22 +0100129}
130#endif