blob: 9e6dc02b61d2947ed69d6eb0969432d51051773d [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
maxims@google.com4dc038f2017-04-17 12:00:30 -07002/*
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
4 * Copyright 2016 IBM Corporation
5 * Copyright 2017 Google, Inc.
maxims@google.com4dc038f2017-04-17 12:00:30 -07006 */
7
8#include <common.h>
9#include <clk.h>
10#include <dm.h>
11#include <errno.h>
12#include <fdtdec.h>
13#include <i2c.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060014#include <log.h>
maxims@google.com4dc038f2017-04-17 12:00:30 -070015#include <asm/io.h>
16#include <asm/arch/scu_ast2500.h>
Simon Glass61b29b82020-02-03 07:36:15 -070017#include <linux/err.h>
maxims@google.com4dc038f2017-04-17 12:00:30 -070018
19#include "ast_i2c.h"
20
21#define I2C_TIMEOUT_US 100000
22#define I2C_SLEEP_STEP_US 20
23
24#define HIGHSPEED_TTIMEOUT 3
25
maxims@google.com4dc038f2017-04-17 12:00:30 -070026/*
27 * Device private data
28 */
29struct ast_i2c_priv {
30 /* This device's clock */
31 struct clk clk;
32 /* Device registers */
33 struct ast_i2c_regs *regs;
34 /* I2C speed in Hz */
35 int speed;
36};
37
38/*
39 * Given desired divider ratio, return the value that needs to be set
40 * in Clock and AC Timing Control register
41 */
42static u32 get_clk_reg_val(ulong divider_ratio)
43{
44 ulong inc = 0, div;
45 ulong scl_low, scl_high, data;
46
47 for (div = 0; divider_ratio >= 16; div++) {
48 inc |= (divider_ratio & 1);
49 divider_ratio >>= 1;
50 }
51 divider_ratio += inc;
52 scl_low = (divider_ratio >> 1) - 1;
53 scl_high = divider_ratio - scl_low - 2;
54 data = I2CD_CACTC_BASE
55 | (scl_high << I2CD_TCKHIGH_SHIFT)
56 | (scl_low << I2CD_TCKLOW_SHIFT)
57 | (div << I2CD_BASE_DIV_SHIFT);
58
59 return data;
60}
61
62static void ast_i2c_clear_interrupts(struct udevice *dev)
63{
64 struct ast_i2c_priv *priv = dev_get_priv(dev);
65
66 writel(~0, &priv->regs->isr);
67}
68
69static void ast_i2c_init_bus(struct udevice *dev)
70{
71 struct ast_i2c_priv *priv = dev_get_priv(dev);
72
73 /* Reset device */
74 writel(0, &priv->regs->fcr);
75 /* Enable Master Mode. Assuming single-master */
76 writel(I2CD_MASTER_EN
77 | I2CD_M_SDA_LOCK_EN
78 | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
79 &priv->regs->fcr);
80 /* Enable Interrupts */
81 writel(I2CD_INTR_TX_ACK
82 | I2CD_INTR_TX_NAK
83 | I2CD_INTR_RX_DONE
84 | I2CD_INTR_BUS_RECOVER_DONE
85 | I2CD_INTR_NORMAL_STOP
86 | I2CD_INTR_ABNORMAL, &priv->regs->icr);
87}
88
89static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
90{
91 struct ast_i2c_priv *priv = dev_get_priv(dev);
92 int ret;
93
Simon Glassa821c4a2017-05-17 17:18:05 -060094 priv->regs = devfdt_get_addr_ptr(dev);
maxims@google.com4dc038f2017-04-17 12:00:30 -070095 if (IS_ERR(priv->regs))
96 return PTR_ERR(priv->regs);
97
98 ret = clk_get_by_index(dev, 0, &priv->clk);
99 if (ret < 0) {
100 debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
101 ret);
102 return ret;
103 }
104
105 return 0;
106}
107
108static int ast_i2c_probe(struct udevice *dev)
109{
110 struct ast2500_scu *scu;
111
112 debug("Enabling I2C%u\n", dev->seq);
113
114 /*
115 * Get all I2C devices out of Reset.
116 * Only needs to be done once, but doing it for every
117 * device does not hurt.
118 */
119 scu = ast_get_scu();
120 ast_scu_unlock(scu);
121 clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
122 ast_scu_lock(scu);
123
124 ast_i2c_init_bus(dev);
125
126 return 0;
127}
128
129static int ast_i2c_wait_isr(struct udevice *dev, u32 flag)
130{
131 struct ast_i2c_priv *priv = dev_get_priv(dev);
132 int timeout = I2C_TIMEOUT_US;
133
134 while (!(readl(&priv->regs->isr) & flag) && timeout > 0) {
135 udelay(I2C_SLEEP_STEP_US);
136 timeout -= I2C_SLEEP_STEP_US;
137 }
138
139 ast_i2c_clear_interrupts(dev);
140 if (timeout <= 0)
141 return -ETIMEDOUT;
142
143 return 0;
144}
145
146static int ast_i2c_send_stop(struct udevice *dev)
147{
148 struct ast_i2c_priv *priv = dev_get_priv(dev);
149
150 writel(I2CD_M_STOP_CMD, &priv->regs->csr);
151
152 return ast_i2c_wait_isr(dev, I2CD_INTR_NORMAL_STOP);
153}
154
155static int ast_i2c_wait_tx(struct udevice *dev)
156{
157 struct ast_i2c_priv *priv = dev_get_priv(dev);
158 int timeout = I2C_TIMEOUT_US;
159 u32 flag = I2CD_INTR_TX_ACK | I2CD_INTR_TX_NAK;
160 u32 status = readl(&priv->regs->isr) & flag;
161 int ret = 0;
162
163 while (!status && timeout > 0) {
164 status = readl(&priv->regs->isr) & flag;
165 udelay(I2C_SLEEP_STEP_US);
166 timeout -= I2C_SLEEP_STEP_US;
167 }
168
169 if (status == I2CD_INTR_TX_NAK)
170 ret = -EREMOTEIO;
171
172 if (timeout <= 0)
173 ret = -ETIMEDOUT;
174
175 ast_i2c_clear_interrupts(dev);
176
177 return ret;
178}
179
180static int ast_i2c_start_txn(struct udevice *dev, uint devaddr)
181{
182 struct ast_i2c_priv *priv = dev_get_priv(dev);
183
184 /* Start and Send Device Address */
185 writel(devaddr, &priv->regs->trbbr);
186 writel(I2CD_M_START_CMD | I2CD_M_TX_CMD, &priv->regs->csr);
187
188 return ast_i2c_wait_tx(dev);
189}
190
191static int ast_i2c_read_data(struct udevice *dev, u8 chip_addr, u8 *buffer,
192 size_t len, bool send_stop)
193{
194 struct ast_i2c_priv *priv = dev_get_priv(dev);
195 u32 i2c_cmd = I2CD_M_RX_CMD;
196 int ret;
197
198 ret = ast_i2c_start_txn(dev, (chip_addr << 1) | I2C_M_RD);
199 if (ret < 0)
200 return ret;
201
202 for (; len > 0; len--, buffer++) {
203 if (len == 1)
204 i2c_cmd |= I2CD_M_S_RX_CMD_LAST;
205 writel(i2c_cmd, &priv->regs->csr);
206 ret = ast_i2c_wait_isr(dev, I2CD_INTR_RX_DONE);
207 if (ret < 0)
208 return ret;
209 *buffer = (readl(&priv->regs->trbbr) & I2CD_RX_DATA_MASK)
210 >> I2CD_RX_DATA_SHIFT;
211 }
212 ast_i2c_clear_interrupts(dev);
213
214 if (send_stop)
215 return ast_i2c_send_stop(dev);
216
217 return 0;
218}
219
220static int ast_i2c_write_data(struct udevice *dev, u8 chip_addr, u8
221 *buffer, size_t len, bool send_stop)
222{
223 struct ast_i2c_priv *priv = dev_get_priv(dev);
224 int ret;
225
226 ret = ast_i2c_start_txn(dev, (chip_addr << 1));
227 if (ret < 0)
228 return ret;
229
230 for (; len > 0; len--, buffer++) {
231 writel(*buffer, &priv->regs->trbbr);
232 writel(I2CD_M_TX_CMD, &priv->regs->csr);
233 ret = ast_i2c_wait_tx(dev);
234 if (ret < 0)
235 return ret;
236 }
237
238 if (send_stop)
239 return ast_i2c_send_stop(dev);
240
241 return 0;
242}
243
244static int ast_i2c_deblock(struct udevice *dev)
245{
246 struct ast_i2c_priv *priv = dev_get_priv(dev);
247 struct ast_i2c_regs *regs = priv->regs;
248 u32 csr = readl(&regs->csr);
249 bool sda_high = csr & I2CD_SDA_LINE_STS;
250 bool scl_high = csr & I2CD_SCL_LINE_STS;
251 int ret = 0;
252
253 if (sda_high && scl_high) {
254 /* Bus is idle, no deblocking needed. */
255 return 0;
256 } else if (sda_high) {
257 /* Send stop command */
258 debug("Unterminated TXN in (%x), sending stop\n", csr);
259 ret = ast_i2c_send_stop(dev);
260 } else if (scl_high) {
261 /* Possibly stuck slave */
262 debug("Bus stuck (%x), attempting recovery\n", csr);
263 writel(I2CD_BUS_RECOVER_CMD, &regs->csr);
264 ret = ast_i2c_wait_isr(dev, I2CD_INTR_BUS_RECOVER_DONE);
265 } else {
266 /* Just try to reinit the device. */
267 ast_i2c_init_bus(dev);
268 }
269
270 return ret;
271}
272
273static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
274{
275 int ret;
276
277 ret = ast_i2c_deblock(dev);
278 if (ret < 0)
279 return ret;
280
281 debug("i2c_xfer: %d messages\n", nmsgs);
282 for (; nmsgs > 0; nmsgs--, msg++) {
283 if (msg->flags & I2C_M_RD) {
284 debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",
285 msg->addr, msg->len, msg->flags);
286 ret = ast_i2c_read_data(dev, msg->addr, msg->buf,
287 msg->len, (nmsgs == 1));
288 } else {
289 debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",
290 msg->addr, msg->len, msg->flags);
291 ret = ast_i2c_write_data(dev, msg->addr, msg->buf,
292 msg->len, (nmsgs == 1));
293 }
294 if (ret) {
295 debug("%s: error (%d)\n", __func__, ret);
296 return -EREMOTEIO;
297 }
298 }
299
300 return 0;
301}
302
303static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)
304{
305 struct ast_i2c_priv *priv = dev_get_priv(dev);
306 struct ast_i2c_regs *regs = priv->regs;
307 ulong i2c_rate, divider;
308
309 debug("Setting speed for I2C%d to <%u>\n", dev->seq, speed);
310 if (!speed) {
311 debug("No valid speed specified\n");
312 return -EINVAL;
313 }
314
315 i2c_rate = clk_get_rate(&priv->clk);
316 divider = i2c_rate / speed;
317
318 priv->speed = speed;
Simon Glass642400c2020-01-23 11:48:17 -0700319 if (speed > I2C_SPEED_FAST_RATE) {
maxims@google.com4dc038f2017-04-17 12:00:30 -0700320 debug("Enable High Speed\n");
321 setbits_le32(&regs->fcr, I2CD_M_HIGH_SPEED_EN
322 | I2CD_M_SDA_DRIVE_1T_EN
323 | I2CD_SDA_DRIVE_1T_EN);
324 writel(HIGHSPEED_TTIMEOUT, &regs->cactcr2);
325 } else {
326 debug("Enabling Normal Speed\n");
327 writel(I2CD_NO_TIMEOUT_CTRL, &regs->cactcr2);
328 }
329
330 writel(get_clk_reg_val(divider), &regs->cactcr1);
331 ast_i2c_clear_interrupts(dev);
332
333 return 0;
334}
335
336static const struct dm_i2c_ops ast_i2c_ops = {
337 .xfer = ast_i2c_xfer,
338 .set_bus_speed = ast_i2c_set_speed,
339 .deblock = ast_i2c_deblock,
340};
341
342static const struct udevice_id ast_i2c_ids[] = {
343 { .compatible = "aspeed,ast2400-i2c-bus" },
344 { .compatible = "aspeed,ast2500-i2c-bus" },
345 { },
346};
347
348U_BOOT_DRIVER(ast_i2c) = {
349 .name = "ast_i2c",
350 .id = UCLASS_I2C,
351 .of_match = ast_i2c_ids,
352 .probe = ast_i2c_probe,
353 .ofdata_to_platdata = ast_i2c_ofdata_to_platdata,
354 .priv_auto_alloc_size = sizeof(struct ast_i2c_priv),
355 .ops = &ast_i2c_ops,
356};