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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Allen Martinb19f5742013-01-29 13:51:28 +00002/*
3 * NVIDIA Tegra SPI-SLINK controller
4 *
5 * Copyright (c) 2010-2013 NVIDIA Corporation
Allen Martinb19f5742013-01-29 13:51:28 +00006 */
7
8#include <common.h>
Simon Glassfda6fac2014-10-13 23:42:13 -06009#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060010#include <log.h>
Simon Glass10453152019-11-14 12:57:30 -070011#include <time.h>
Allen Martinb19f5742013-01-29 13:51:28 +000012#include <asm/io.h>
Allen Martinb19f5742013-01-29 13:51:28 +000013#include <asm/arch/clock.h>
14#include <asm/arch-tegra/clk_rst.h>
Allen Martinb19f5742013-01-29 13:51:28 +000015#include <spi.h>
16#include <fdtdec.h>
Simon Glassfda6fac2014-10-13 23:42:13 -060017#include "tegra_spi.h"
Allen Martinb19f5742013-01-29 13:51:28 +000018
19DECLARE_GLOBAL_DATA_PTR;
20
Allen Martin7a49ba62013-03-16 18:58:05 +000021/* COMMAND */
Jagan Tekif6922482015-10-23 01:39:06 +053022#define SLINK_CMD_ENB BIT(31)
23#define SLINK_CMD_GO BIT(30)
24#define SLINK_CMD_M_S BIT(28)
Mirza Krak5cb1b7b2015-09-08 10:30:49 +020025#define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24)
Jagan Tekif6922482015-10-23 01:39:06 +053026#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24)
Mirza Krak5cb1b7b2015-09-08 10:30:49 +020027#define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24)
28#define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24)
29#define SLINK_CMD_IDLE_SCLK_MASK (3 << 24)
Jagan Tekif6922482015-10-23 01:39:06 +053030#define SLINK_CMD_CK_SDA BIT(21)
31#define SLINK_CMD_CS_POL BIT(13)
32#define SLINK_CMD_CS_VAL BIT(12)
33#define SLINK_CMD_CS_SOFT BIT(11)
34#define SLINK_CMD_BIT_LENGTH BIT(4)
Jagan Teki76538ec2015-10-23 01:03:10 +053035#define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
Allen Martin7a49ba62013-03-16 18:58:05 +000036/* COMMAND2 */
Jagan Tekif6922482015-10-23 01:39:06 +053037#define SLINK_CMD2_TXEN BIT(30)
38#define SLINK_CMD2_RXEN BIT(31)
39#define SLINK_CMD2_SS_EN BIT(18)
Allen Martin7a49ba62013-03-16 18:58:05 +000040#define SLINK_CMD2_SS_EN_SHIFT 18
Jagan Teki76538ec2015-10-23 01:03:10 +053041#define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18)
Jagan Tekif6922482015-10-23 01:39:06 +053042#define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17)
Allen Martin7a49ba62013-03-16 18:58:05 +000043/* STATUS */
Jagan Tekif6922482015-10-23 01:39:06 +053044#define SLINK_STAT_BSY BIT(31)
45#define SLINK_STAT_RDY BIT(30)
46#define SLINK_STAT_ERR BIT(29)
47#define SLINK_STAT_RXF_FLUSH BIT(27)
48#define SLINK_STAT_TXF_FLUSH BIT(26)
49#define SLINK_STAT_RXF_OVF BIT(25)
50#define SLINK_STAT_TXF_UNR BIT(24)
51#define SLINK_STAT_RXF_EMPTY BIT(23)
52#define SLINK_STAT_RXF_FULL BIT(22)
53#define SLINK_STAT_TXF_EMPTY BIT(21)
54#define SLINK_STAT_TXF_FULL BIT(20)
55#define SLINK_STAT_TXF_OVF BIT(19)
56#define SLINK_STAT_RXF_UNR BIT(18)
57#define SLINK_STAT_CUR_BLKCNT BIT(15)
Allen Martin7a49ba62013-03-16 18:58:05 +000058/* STATUS2 */
Jagan Tekif6922482015-10-23 01:39:06 +053059#define SLINK_STAT2_RXF_FULL_CNT BIT(16)
60#define SLINK_STAT2_TXF_FULL_CNT BIT(0)
Allen Martin7a49ba62013-03-16 18:58:05 +000061
62#define SPI_TIMEOUT 1000
63#define TEGRA_SPI_MAX_FREQ 52000000
64
65struct spi_regs {
66 u32 command; /* SLINK_COMMAND_0 register */
67 u32 command2; /* SLINK_COMMAND2_0 reg */
68 u32 status; /* SLINK_STATUS_0 register */
69 u32 reserved; /* Reserved offset 0C */
70 u32 mas_data; /* SLINK_MAS_DATA_0 reg */
71 u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
72 u32 dma_ctl; /* SLINK_DMA_CTL_0 register */
73 u32 status2; /* SLINK_STATUS2_0 reg */
74 u32 rsvd[56]; /* 0x20 to 0xFF reserved */
75 u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */
76 u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
77 u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
78};
79
Simon Glassfda6fac2014-10-13 23:42:13 -060080struct tegra30_spi_priv {
Allen Martin7a49ba62013-03-16 18:58:05 +000081 struct spi_regs *regs;
Allen Martinb19f5742013-01-29 13:51:28 +000082 unsigned int freq;
83 unsigned int mode;
84 int periph_id;
85 int valid;
Simon Glassfda6fac2014-10-13 23:42:13 -060086 int last_transaction_us;
Allen Martinb19f5742013-01-29 13:51:28 +000087};
88
89struct tegra_spi_slave {
90 struct spi_slave slave;
Simon Glassfda6fac2014-10-13 23:42:13 -060091 struct tegra30_spi_priv *ctrl;
Allen Martinb19f5742013-01-29 13:51:28 +000092};
93
Simon Glassfda6fac2014-10-13 23:42:13 -060094static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
Allen Martinb19f5742013-01-29 13:51:28 +000095{
Simon Glassfda6fac2014-10-13 23:42:13 -060096 struct tegra_spi_platdata *plat = bus->platdata;
97 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -070098 int node = dev_of_offset(bus);
Simon Glassfda6fac2014-10-13 23:42:13 -060099
Simon Glassa821c4a2017-05-17 17:18:05 -0600100 plat->base = devfdt_get_addr(bus);
Simon Glass000f15f2017-07-25 08:30:00 -0600101 plat->periph_id = clock_decode_periph_id(bus);
Simon Glassfda6fac2014-10-13 23:42:13 -0600102
103 if (plat->periph_id == PERIPH_ID_NONE) {
104 debug("%s: could not decode periph id %d\n", __func__,
105 plat->periph_id);
106 return -FDT_ERR_NOTFOUND;
107 }
108
109 /* Use 500KHz as a suitable default */
110 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
111 500000);
112 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
113 "spi-deactivate-delay", 0);
114 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
115 __func__, plat->base, plat->periph_id, plat->frequency,
116 plat->deactivate_delay_us);
117
118 return 0;
Allen Martinb19f5742013-01-29 13:51:28 +0000119}
120
Simon Glassfda6fac2014-10-13 23:42:13 -0600121static int tegra30_spi_probe(struct udevice *bus)
Allen Martinb19f5742013-01-29 13:51:28 +0000122{
Simon Glassfda6fac2014-10-13 23:42:13 -0600123 struct tegra_spi_platdata *plat = dev_get_platdata(bus);
124 struct tegra30_spi_priv *priv = dev_get_priv(bus);
125
126 priv->regs = (struct spi_regs *)plat->base;
127
128 priv->last_transaction_us = timer_get_us();
129 priv->freq = plat->frequency;
130 priv->periph_id = plat->periph_id;
131
Stephen Warren4832c7f2016-08-18 10:53:33 -0600132 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
133 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
134 priv->freq);
135
Simon Glassfda6fac2014-10-13 23:42:13 -0600136 return 0;
Allen Martinb19f5742013-01-29 13:51:28 +0000137}
138
Simon Glass9694b722015-04-19 09:05:40 -0600139static int tegra30_spi_claim_bus(struct udevice *dev)
Allen Martinb19f5742013-01-29 13:51:28 +0000140{
Simon Glass9694b722015-04-19 09:05:40 -0600141 struct udevice *bus = dev->parent;
Simon Glassfda6fac2014-10-13 23:42:13 -0600142 struct tegra30_spi_priv *priv = dev_get_priv(bus);
143 struct spi_regs *regs = priv->regs;
Allen Martinb19f5742013-01-29 13:51:28 +0000144 u32 reg;
145
146 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
Simon Glassfda6fac2014-10-13 23:42:13 -0600147 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
148 priv->freq);
Allen Martinb19f5742013-01-29 13:51:28 +0000149
150 /* Clear stale status here */
151 reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
152 SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
153 writel(reg, &regs->status);
154 debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
155
156 /* Set master mode and sw controlled CS */
157 reg = readl(&regs->command);
158 reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
159 writel(reg, &regs->command);
160 debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
161
162 return 0;
163}
164
Simon Glassfda6fac2014-10-13 23:42:13 -0600165static void spi_cs_activate(struct udevice *dev)
Allen Martinb19f5742013-01-29 13:51:28 +0000166{
Simon Glassfda6fac2014-10-13 23:42:13 -0600167 struct udevice *bus = dev->parent;
168 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
169 struct tegra30_spi_priv *priv = dev_get_priv(bus);
170
171 /* If it's too soon to do another transaction, wait */
172 if (pdata->deactivate_delay_us &&
173 priv->last_transaction_us) {
174 ulong delay_us; /* The delay completed so far */
175 delay_us = timer_get_us() - priv->last_transaction_us;
176 if (delay_us < pdata->deactivate_delay_us)
177 udelay(pdata->deactivate_delay_us - delay_us);
178 }
Allen Martinb19f5742013-01-29 13:51:28 +0000179
180 /* CS is negated on Tegra, so drive a 1 to get a 0 */
Simon Glassfda6fac2014-10-13 23:42:13 -0600181 setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
Allen Martinb19f5742013-01-29 13:51:28 +0000182}
183
Simon Glassfda6fac2014-10-13 23:42:13 -0600184static void spi_cs_deactivate(struct udevice *dev)
Allen Martinb19f5742013-01-29 13:51:28 +0000185{
Simon Glassfda6fac2014-10-13 23:42:13 -0600186 struct udevice *bus = dev->parent;
187 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
188 struct tegra30_spi_priv *priv = dev_get_priv(bus);
Allen Martinb19f5742013-01-29 13:51:28 +0000189
190 /* CS is negated on Tegra, so drive a 0 to get a 1 */
Simon Glassfda6fac2014-10-13 23:42:13 -0600191 clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
192
193 /* Remember time of this transaction so we can honour the bus delay */
194 if (pdata->deactivate_delay_us)
195 priv->last_transaction_us = timer_get_us();
Allen Martinb19f5742013-01-29 13:51:28 +0000196}
197
Simon Glassfda6fac2014-10-13 23:42:13 -0600198static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
199 const void *data_out, void *data_in,
200 unsigned long flags)
Allen Martinb19f5742013-01-29 13:51:28 +0000201{
Simon Glassfda6fac2014-10-13 23:42:13 -0600202 struct udevice *bus = dev->parent;
203 struct tegra30_spi_priv *priv = dev_get_priv(bus);
204 struct spi_regs *regs = priv->regs;
Allen Martinb19f5742013-01-29 13:51:28 +0000205 u32 reg, tmpdout, tmpdin = 0;
206 const u8 *dout = data_out;
207 u8 *din = data_in;
208 int num_bytes;
209 int ret;
210
211 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
Simon Glassfda6fac2014-10-13 23:42:13 -0600212 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
Allen Martinb19f5742013-01-29 13:51:28 +0000213 if (bitlen % 8)
214 return -1;
215 num_bytes = bitlen / 8;
216
217 ret = 0;
218
219 reg = readl(&regs->status);
220 writel(reg, &regs->status); /* Clear all SPI events via R/W */
221 debug("%s entry: STATUS = %08x\n", __func__, reg);
222
223 reg = readl(&regs->status2);
224 writel(reg, &regs->status2); /* Clear all STATUS2 events via R/W */
225 debug("%s entry: STATUS2 = %08x\n", __func__, reg);
226
227 debug("%s entry: COMMAND = %08x\n", __func__, readl(&regs->command));
228
229 clrsetbits_le32(&regs->command2, SLINK_CMD2_SS_EN_MASK,
230 SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
Simon Glassfda6fac2014-10-13 23:42:13 -0600231 (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT));
Allen Martinb19f5742013-01-29 13:51:28 +0000232 debug("%s entry: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
233
234 if (flags & SPI_XFER_BEGIN)
Simon Glassfda6fac2014-10-13 23:42:13 -0600235 spi_cs_activate(dev);
Allen Martinb19f5742013-01-29 13:51:28 +0000236
237 /* handle data in 32-bit chunks */
238 while (num_bytes > 0) {
239 int bytes;
240 int is_read = 0;
241 int tm, i;
242
243 tmpdout = 0;
244 bytes = (num_bytes > 4) ? 4 : num_bytes;
245
246 if (dout != NULL) {
247 for (i = 0; i < bytes; ++i)
248 tmpdout = (tmpdout << 8) | dout[i];
249 dout += bytes;
250 }
251
252 num_bytes -= bytes;
253
254 clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
255 bytes * 8 - 1);
256 writel(tmpdout, &regs->tx_fifo);
257 setbits_le32(&regs->command, SLINK_CMD_GO);
258
259 /*
260 * Wait for SPI transmit FIFO to empty, or to time out.
261 * The RX FIFO status will be read and cleared last
262 */
263 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
264 u32 status;
265
266 status = readl(&regs->status);
267
268 /* We can exit when we've had both RX and TX activity */
269 if (is_read && (status & SLINK_STAT_TXF_EMPTY))
270 break;
271
272 if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
273 SLINK_STAT_RDY)
274 tm++;
275
276 else if (!(status & SLINK_STAT_RXF_EMPTY)) {
277 tmpdin = readl(&regs->rx_fifo);
278 is_read = 1;
279
280 /* swap bytes read in */
281 if (din != NULL) {
282 for (i = bytes - 1; i >= 0; --i) {
283 din[i] = tmpdin & 0xff;
284 tmpdin >>= 8;
285 }
286 din += bytes;
287 }
288 }
289 }
290
291 if (tm >= SPI_TIMEOUT)
292 ret = tm;
293
294 /* clear ACK RDY, etc. bits */
295 writel(readl(&regs->status), &regs->status);
296 }
297
298 if (flags & SPI_XFER_END)
Simon Glassfda6fac2014-10-13 23:42:13 -0600299 spi_cs_deactivate(dev);
Allen Martinb19f5742013-01-29 13:51:28 +0000300
301 debug("%s: transfer ended. Value=%08x, status = %08x\n",
302 __func__, tmpdin, readl(&regs->status));
303
304 if (ret) {
305 printf("%s: timeout during SPI transfer, tm %d\n",
306 __func__, ret);
307 return -1;
308 }
309
310 return 0;
311}
Simon Glassfda6fac2014-10-13 23:42:13 -0600312
313static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
314{
315 struct tegra_spi_platdata *plat = bus->platdata;
316 struct tegra30_spi_priv *priv = dev_get_priv(bus);
317
318 if (speed > plat->frequency)
319 speed = plat->frequency;
320 priv->freq = speed;
321 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
322
323 return 0;
324}
325
326static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
327{
328 struct tegra30_spi_priv *priv = dev_get_priv(bus);
Mirza Krak5cb1b7b2015-09-08 10:30:49 +0200329 struct spi_regs *regs = priv->regs;
330 u32 reg;
331
332 reg = readl(&regs->command);
333
334 /* Set CPOL and CPHA */
335 reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA);
336 if (mode & SPI_CPHA)
337 reg |= SLINK_CMD_CK_SDA;
338
339 if (mode & SPI_CPOL)
340 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH;
341 else
342 reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW;
343
344 writel(reg, &regs->command);
Simon Glassfda6fac2014-10-13 23:42:13 -0600345
346 priv->mode = mode;
347 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
348
349 return 0;
350}
351
352static const struct dm_spi_ops tegra30_spi_ops = {
353 .claim_bus = tegra30_spi_claim_bus,
354 .xfer = tegra30_spi_xfer,
355 .set_speed = tegra30_spi_set_speed,
356 .set_mode = tegra30_spi_set_mode,
357 /*
358 * cs_info is not needed, since we require all chip selects to be
359 * in the device tree explicitly
360 */
361};
362
363static const struct udevice_id tegra30_spi_ids[] = {
364 { .compatible = "nvidia,tegra20-slink" },
365 { }
366};
367
368U_BOOT_DRIVER(tegra30_spi) = {
369 .name = "tegra20_slink",
370 .id = UCLASS_SPI,
371 .of_match = tegra30_spi_ids,
372 .ops = &tegra30_spi_ops,
373 .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata,
374 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
375 .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv),
Simon Glassfda6fac2014-10-13 23:42:13 -0600376 .probe = tegra30_spi_probe,
377};