blob: 82fea742b06b394ec84338b6f64018e6ef23771b [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass291391b2011-06-13 16:13:09 -07002/*
Simon Glass0990fcb2015-07-07 20:53:42 -06003 * Copyright (c) 2015 Google, Inc
Simon Glass291391b2011-06-13 16:13:09 -07004 * Copyright (c) 2011 The Chromium OS Authors.
5 * Copyright (C) 2009 NVIDIA, Corporation
Simon Glassad6e48e2014-09-08 13:44:14 -06006 * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
Simon Glass291391b2011-06-13 16:13:09 -07007 */
8
9#include <common.h>
Simon Glass0990fcb2015-07-07 20:53:42 -060010#include <dm.h>
Simon Glassa2692592015-07-07 20:53:38 -060011#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Simon Glassa2692592015-07-07 20:53:38 -060013#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060014#include <memalign.h>
Simon Glass90526e92020-05-10 11:39:56 -060015#include <net.h>
Simon Glass291391b2011-06-13 16:13:09 -070016#include <usb.h>
Simon Glassa2692592015-07-07 20:53:38 -060017#include <asm/unaligned.h>
Simon Glass291391b2011-06-13 16:13:09 -070018#include <linux/mii.h>
19#include "usb_ether.h"
20
21/* SMSC LAN95xx based USB 2.0 Ethernet Devices */
22
Suriyan Ramasami98f686c2013-10-07 20:30:58 -070023/* LED defines */
24#define LED_GPIO_CFG (0x24)
25#define LED_GPIO_CFG_SPD_LED (0x01000000)
26#define LED_GPIO_CFG_LNK_LED (0x00100000)
27#define LED_GPIO_CFG_FDX_LED (0x00010000)
28
Simon Glass291391b2011-06-13 16:13:09 -070029/* Tx command words */
30#define TX_CMD_A_FIRST_SEG_ 0x00002000
31#define TX_CMD_A_LAST_SEG_ 0x00001000
32
33/* Rx status word */
34#define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
35#define RX_STS_ES_ 0x00008000 /* Error Summary */
36
37/* SCSRs */
38#define ID_REV 0x00
39
40#define INT_STS 0x08
41
42#define TX_CFG 0x10
43#define TX_CFG_ON_ 0x00000004
44
45#define HW_CFG 0x14
46#define HW_CFG_BIR_ 0x00001000
47#define HW_CFG_RXDOFF_ 0x00000600
48#define HW_CFG_MEF_ 0x00000020
49#define HW_CFG_BCE_ 0x00000002
50#define HW_CFG_LRST_ 0x00000008
51
52#define PM_CTRL 0x20
53#define PM_CTL_PHY_RST_ 0x00000010
54
55#define AFC_CFG 0x2C
56
57/*
58 * Hi watermark = 15.5Kb (~10 mtu pkts)
59 * low watermark = 3k (~2 mtu pkts)
60 * backpressure duration = ~ 350us
61 * Apply FC on any frame.
62 */
63#define AFC_CFG_DEFAULT 0x00F830A1
64
65#define E2P_CMD 0x30
66#define E2P_CMD_BUSY_ 0x80000000
67#define E2P_CMD_READ_ 0x00000000
68#define E2P_CMD_TIMEOUT_ 0x00000400
69#define E2P_CMD_LOADED_ 0x00000200
70#define E2P_CMD_ADDR_ 0x000001FF
71
72#define E2P_DATA 0x34
73
74#define BURST_CAP 0x38
75
76#define INT_EP_CTL 0x68
77#define INT_EP_CTL_PHY_INT_ 0x00008000
78
79#define BULK_IN_DLY 0x6C
80
81/* MAC CSRs */
82#define MAC_CR 0x100
83#define MAC_CR_MCPAS_ 0x00080000
84#define MAC_CR_PRMS_ 0x00040000
85#define MAC_CR_HPFILT_ 0x00002000
86#define MAC_CR_TXEN_ 0x00000008
87#define MAC_CR_RXEN_ 0x00000004
88
89#define ADDRH 0x104
90
91#define ADDRL 0x108
92
93#define MII_ADDR 0x114
94#define MII_WRITE_ 0x02
95#define MII_BUSY_ 0x01
96#define MII_READ_ 0x00 /* ~of MII Write bit */
97
98#define MII_DATA 0x118
99
100#define FLOW 0x11C
101
102#define VLAN1 0x120
103
104#define COE_CR 0x130
105#define Tx_COE_EN_ 0x00010000
106#define Rx_COE_EN_ 0x00000001
107
108/* Vendor-specific PHY Definitions */
109#define PHY_INT_SRC 29
110
111#define PHY_INT_MASK 30
112#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
113#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
114#define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
115 PHY_INT_MASK_LINK_DOWN_)
116
117/* USB Vendor Requests */
118#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
119#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
120
121/* Some extra defines */
122#define HS_USB_PKT_SIZE 512
123#define FS_USB_PKT_SIZE 64
Stefan Brüns0d2837c2015-08-30 17:59:45 +0200124/* 5/33 is lower limit for BURST_CAP to work */
125#define DEFAULT_HS_BURST_CAP_SIZE (5 * HS_USB_PKT_SIZE)
126#define DEFAULT_FS_BURST_CAP_SIZE (33 * FS_USB_PKT_SIZE)
Simon Glass291391b2011-06-13 16:13:09 -0700127#define DEFAULT_BULK_IN_DELAY 0x00002000
128#define MAX_SINGLE_PACKET_SIZE 2048
129#define EEPROM_MAC_OFFSET 0x01
130#define SMSC95XX_INTERNAL_PHY_ID 1
131#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
132
133/* local defines */
134#define SMSC95XX_BASE_NAME "sms"
135#define USB_CTRL_SET_TIMEOUT 5000
136#define USB_CTRL_GET_TIMEOUT 5000
137#define USB_BULK_SEND_TIMEOUT 5000
138#define USB_BULK_RECV_TIMEOUT 5000
139
Stefan Brüns0d2837c2015-08-30 17:59:45 +0200140#define RX_URB_SIZE DEFAULT_HS_BURST_CAP_SIZE
Simon Glass291391b2011-06-13 16:13:09 -0700141#define PHY_CONNECT_TIMEOUT 5000
142
143#define TURBO_MODE
144
Simon Glass0990fcb2015-07-07 20:53:42 -0600145#ifndef CONFIG_DM_ETH
Simon Glass291391b2011-06-13 16:13:09 -0700146/* local vars */
147static int curr_eth_dev; /* index for name of next device detected */
Simon Glass0990fcb2015-07-07 20:53:42 -0600148#endif
Simon Glass291391b2011-06-13 16:13:09 -0700149
Lucas Stache1dbdf92012-08-22 11:04:57 +0000150/* driver private */
151struct smsc95xx_private {
Simon Glass0990fcb2015-07-07 20:53:42 -0600152#ifdef CONFIG_DM_ETH
153 struct ueth_data ueth;
154#endif
Lucas Stache1dbdf92012-08-22 11:04:57 +0000155 size_t rx_urb_size; /* maximum USB URB size */
156 u32 mac_cr; /* MAC control register value */
157 int have_hwaddr; /* 1 if we have a hardware MAC address */
158};
Simon Glass291391b2011-06-13 16:13:09 -0700159
160/*
161 * Smsc95xx infrastructure commands
162 */
Simon Glass527298c2015-07-07 20:53:41 -0600163static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
Simon Glass291391b2011-06-13 16:13:09 -0700164{
165 int len;
Ilya Yanoke3b31c82012-07-15 04:43:53 +0000166 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
Simon Glass291391b2011-06-13 16:13:09 -0700167
168 cpu_to_le32s(&data);
Ilya Yanoke3b31c82012-07-15 04:43:53 +0000169 tmpbuf[0] = data;
Simon Glass291391b2011-06-13 16:13:09 -0700170
Simon Glass527298c2015-07-07 20:53:41 -0600171 len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
172 USB_VENDOR_REQUEST_WRITE_REGISTER,
173 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
174 0, index, tmpbuf, sizeof(data),
175 USB_CTRL_SET_TIMEOUT);
Simon Glass291391b2011-06-13 16:13:09 -0700176 if (len != sizeof(data)) {
177 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
178 index, data, len);
Simon Glass25a9e982015-07-07 20:53:40 -0600179 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700180 }
181 return 0;
182}
183
Simon Glass527298c2015-07-07 20:53:41 -0600184static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
Simon Glass291391b2011-06-13 16:13:09 -0700185{
186 int len;
Ilya Yanoke3b31c82012-07-15 04:43:53 +0000187 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
Simon Glass291391b2011-06-13 16:13:09 -0700188
Simon Glass527298c2015-07-07 20:53:41 -0600189 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
190 USB_VENDOR_REQUEST_READ_REGISTER,
191 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
Stephen Warrene320f0b2016-03-22 22:28:16 -0600192 0, index, tmpbuf, sizeof(*data),
Simon Glass527298c2015-07-07 20:53:41 -0600193 USB_CTRL_GET_TIMEOUT);
Ilya Yanoke3b31c82012-07-15 04:43:53 +0000194 *data = tmpbuf[0];
Stephen Warrene320f0b2016-03-22 22:28:16 -0600195 if (len != sizeof(*data)) {
Simon Glass291391b2011-06-13 16:13:09 -0700196 debug("smsc95xx_read_reg failed: index=%d, len=%d",
197 index, len);
Simon Glass25a9e982015-07-07 20:53:40 -0600198 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700199 }
200
201 le32_to_cpus(data);
202 return 0;
203}
204
205/* Loop until the read is completed with timeout */
Simon Glass527298c2015-07-07 20:53:41 -0600206static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
Simon Glass291391b2011-06-13 16:13:09 -0700207{
208 unsigned long start_time = get_timer(0);
209 u32 val;
210
211 do {
Simon Glass527298c2015-07-07 20:53:41 -0600212 smsc95xx_read_reg(udev, MII_ADDR, &val);
Simon Glass291391b2011-06-13 16:13:09 -0700213 if (!(val & MII_BUSY_))
214 return 0;
Simon Glass527298c2015-07-07 20:53:41 -0600215 } while (get_timer(start_time) < 1000);
Simon Glass291391b2011-06-13 16:13:09 -0700216
Simon Glass25a9e982015-07-07 20:53:40 -0600217 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700218}
219
Simon Glass527298c2015-07-07 20:53:41 -0600220static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
Simon Glass291391b2011-06-13 16:13:09 -0700221{
222 u32 val, addr;
223
224 /* confirm MII not busy */
Simon Glass527298c2015-07-07 20:53:41 -0600225 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass291391b2011-06-13 16:13:09 -0700226 debug("MII is busy in smsc95xx_mdio_read\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600227 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700228 }
229
230 /* set the address, index & direction (read from PHY) */
231 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
Simon Glass527298c2015-07-07 20:53:41 -0600232 smsc95xx_write_reg(udev, MII_ADDR, addr);
Simon Glass291391b2011-06-13 16:13:09 -0700233
Simon Glass527298c2015-07-07 20:53:41 -0600234 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass291391b2011-06-13 16:13:09 -0700235 debug("Timed out reading MII reg %02X\n", idx);
Simon Glass25a9e982015-07-07 20:53:40 -0600236 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700237 }
238
Simon Glass527298c2015-07-07 20:53:41 -0600239 smsc95xx_read_reg(udev, MII_DATA, &val);
Simon Glass291391b2011-06-13 16:13:09 -0700240
241 return (u16)(val & 0xFFFF);
242}
243
Simon Glass527298c2015-07-07 20:53:41 -0600244static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
Simon Glass291391b2011-06-13 16:13:09 -0700245 int regval)
246{
247 u32 val, addr;
248
249 /* confirm MII not busy */
Simon Glass527298c2015-07-07 20:53:41 -0600250 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass291391b2011-06-13 16:13:09 -0700251 debug("MII is busy in smsc95xx_mdio_write\n");
252 return;
253 }
254
255 val = regval;
Simon Glass527298c2015-07-07 20:53:41 -0600256 smsc95xx_write_reg(udev, MII_DATA, val);
Simon Glass291391b2011-06-13 16:13:09 -0700257
258 /* set the address, index & direction (write to PHY) */
259 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
Simon Glass527298c2015-07-07 20:53:41 -0600260 smsc95xx_write_reg(udev, MII_ADDR, addr);
Simon Glass291391b2011-06-13 16:13:09 -0700261
Simon Glass527298c2015-07-07 20:53:41 -0600262 if (smsc95xx_phy_wait_not_busy(udev))
Simon Glass291391b2011-06-13 16:13:09 -0700263 debug("Timed out writing MII reg %02X\n", idx);
264}
265
Simon Glass527298c2015-07-07 20:53:41 -0600266static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
Simon Glass291391b2011-06-13 16:13:09 -0700267{
268 unsigned long start_time = get_timer(0);
269 u32 val;
270
271 do {
Simon Glass527298c2015-07-07 20:53:41 -0600272 smsc95xx_read_reg(udev, E2P_CMD, &val);
Simon Glass291391b2011-06-13 16:13:09 -0700273 if (!(val & E2P_CMD_BUSY_))
274 return 0;
275 udelay(40);
276 } while (get_timer(start_time) < 1 * 1000 * 1000);
277
278 debug("EEPROM is busy\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600279 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700280}
281
Simon Glass527298c2015-07-07 20:53:41 -0600282static int smsc95xx_wait_eeprom(struct usb_device *udev)
Simon Glass291391b2011-06-13 16:13:09 -0700283{
284 unsigned long start_time = get_timer(0);
285 u32 val;
286
287 do {
Simon Glass527298c2015-07-07 20:53:41 -0600288 smsc95xx_read_reg(udev, E2P_CMD, &val);
Simon Glass291391b2011-06-13 16:13:09 -0700289 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
290 break;
291 udelay(40);
292 } while (get_timer(start_time) < 1 * 1000 * 1000);
293
294 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
295 debug("EEPROM read operation timeout\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600296 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700297 }
298 return 0;
299}
300
Simon Glass527298c2015-07-07 20:53:41 -0600301static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
Simon Glass291391b2011-06-13 16:13:09 -0700302 u8 *data)
303{
304 u32 val;
305 int i, ret;
306
Simon Glass527298c2015-07-07 20:53:41 -0600307 ret = smsc95xx_eeprom_confirm_not_busy(udev);
Simon Glass291391b2011-06-13 16:13:09 -0700308 if (ret)
309 return ret;
310
311 for (i = 0; i < length; i++) {
312 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
Simon Glass527298c2015-07-07 20:53:41 -0600313 smsc95xx_write_reg(udev, E2P_CMD, val);
Simon Glass291391b2011-06-13 16:13:09 -0700314
Simon Glass527298c2015-07-07 20:53:41 -0600315 ret = smsc95xx_wait_eeprom(udev);
Simon Glass291391b2011-06-13 16:13:09 -0700316 if (ret < 0)
317 return ret;
318
Simon Glass527298c2015-07-07 20:53:41 -0600319 smsc95xx_read_reg(udev, E2P_DATA, &val);
Simon Glass291391b2011-06-13 16:13:09 -0700320 data[i] = val & 0xFF;
321 offset++;
322 }
323 return 0;
324}
325
326/*
327 * mii_nway_restart - restart NWay (autonegotiation) for this interface
328 *
329 * Returns 0 on success, negative on error.
330 */
Simon Glass527298c2015-07-07 20:53:41 -0600331static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
Simon Glass291391b2011-06-13 16:13:09 -0700332{
333 int bmcr;
334 int r = -1;
335
336 /* if autoneg is off, it's an error */
Simon Glass527298c2015-07-07 20:53:41 -0600337 bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
Simon Glass291391b2011-06-13 16:13:09 -0700338
339 if (bmcr & BMCR_ANENABLE) {
340 bmcr |= BMCR_ANRESTART;
Simon Glass527298c2015-07-07 20:53:41 -0600341 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
Simon Glass291391b2011-06-13 16:13:09 -0700342 r = 0;
343 }
344 return r;
345}
346
Simon Glass527298c2015-07-07 20:53:41 -0600347static int smsc95xx_phy_initialize(struct usb_device *udev,
348 struct ueth_data *dev)
Simon Glass291391b2011-06-13 16:13:09 -0700349{
Simon Glass527298c2015-07-07 20:53:41 -0600350 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
351 smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
352 ADVERTISE_ALL | ADVERTISE_CSMA |
353 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Simon Glass291391b2011-06-13 16:13:09 -0700354
355 /* read to clear */
Simon Glass527298c2015-07-07 20:53:41 -0600356 smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
Simon Glass291391b2011-06-13 16:13:09 -0700357
Simon Glass527298c2015-07-07 20:53:41 -0600358 smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
359 PHY_INT_MASK_DEFAULT_);
360 mii_nway_restart(udev, dev);
Simon Glass291391b2011-06-13 16:13:09 -0700361
362 debug("phy initialised succesfully\n");
363 return 0;
364}
365
Simon Glass527298c2015-07-07 20:53:41 -0600366static int smsc95xx_init_mac_address(unsigned char *enetaddr,
367 struct usb_device *udev)
Simon Glass291391b2011-06-13 16:13:09 -0700368{
Simon Glass527298c2015-07-07 20:53:41 -0600369 int ret;
370
Simon Glass291391b2011-06-13 16:13:09 -0700371 /* try reading mac address from EEPROM */
Simon Glass527298c2015-07-07 20:53:41 -0600372 ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
373 if (ret)
374 return ret;
375
376 if (is_valid_ethaddr(enetaddr)) {
377 /* eeprom values are valid so use them */
378 debug("MAC address read from EEPROM\n");
379 return 0;
Simon Glass291391b2011-06-13 16:13:09 -0700380 }
381
382 /*
383 * No eeprom, or eeprom values are invalid. Generating a random MAC
384 * address is not safe. Just return an error.
385 */
Simon Glass25a9e982015-07-07 20:53:40 -0600386 debug("Invalid MAC address read from EEPROM\n");
387
388 return -ENXIO;
Simon Glass291391b2011-06-13 16:13:09 -0700389}
390
Simon Glass527298c2015-07-07 20:53:41 -0600391static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
392 struct smsc95xx_private *priv,
393 unsigned char *enetaddr)
Simon Glass291391b2011-06-13 16:13:09 -0700394{
Chris Packham70f14632016-07-13 09:52:36 +1200395 u32 addr_lo = get_unaligned_le32(&enetaddr[0]);
396 u32 addr_hi = get_unaligned_le16(&enetaddr[4]);
Simon Glass291391b2011-06-13 16:13:09 -0700397 int ret;
398
399 /* set hardware address */
400 debug("** %s()\n", __func__);
Simon Glass527298c2015-07-07 20:53:41 -0600401 ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
Wolfgang Grandegger0d9679e2011-11-14 23:19:15 +0000402 if (ret < 0)
Simon Glass291391b2011-06-13 16:13:09 -0700403 return ret;
Simon Glass291391b2011-06-13 16:13:09 -0700404
Simon Glass527298c2015-07-07 20:53:41 -0600405 ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
Simon Glass291391b2011-06-13 16:13:09 -0700406 if (ret < 0)
407 return ret;
Wolfgang Grandegger0d9679e2011-11-14 23:19:15 +0000408
Simon Glass527298c2015-07-07 20:53:41 -0600409 debug("MAC %pM\n", enetaddr);
Lucas Stache1dbdf92012-08-22 11:04:57 +0000410 priv->have_hwaddr = 1;
Simon Glass527298c2015-07-07 20:53:41 -0600411
Simon Glass291391b2011-06-13 16:13:09 -0700412 return 0;
413}
414
415/* Enable or disable Tx & Rx checksum offload engines */
Simon Glass527298c2015-07-07 20:53:41 -0600416static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
417 int use_rx_csum)
Simon Glass291391b2011-06-13 16:13:09 -0700418{
419 u32 read_buf;
Simon Glass527298c2015-07-07 20:53:41 -0600420 int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700421 if (ret < 0)
422 return ret;
423
424 if (use_tx_csum)
425 read_buf |= Tx_COE_EN_;
426 else
427 read_buf &= ~Tx_COE_EN_;
428
429 if (use_rx_csum)
430 read_buf |= Rx_COE_EN_;
431 else
432 read_buf &= ~Rx_COE_EN_;
433
Simon Glass527298c2015-07-07 20:53:41 -0600434 ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700435 if (ret < 0)
436 return ret;
437
438 debug("COE_CR = 0x%08x\n", read_buf);
439 return 0;
440}
441
Simon Glass527298c2015-07-07 20:53:41 -0600442static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
Simon Glass291391b2011-06-13 16:13:09 -0700443{
444 /* No multicast in u-boot */
Lucas Stache1dbdf92012-08-22 11:04:57 +0000445 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
Simon Glass291391b2011-06-13 16:13:09 -0700446}
447
448/* starts the TX path */
Simon Glass527298c2015-07-07 20:53:41 -0600449static void smsc95xx_start_tx_path(struct usb_device *udev,
450 struct smsc95xx_private *priv)
Simon Glass291391b2011-06-13 16:13:09 -0700451{
452 u32 reg_val;
453
454 /* Enable Tx at MAC */
Lucas Stache1dbdf92012-08-22 11:04:57 +0000455 priv->mac_cr |= MAC_CR_TXEN_;
Simon Glass291391b2011-06-13 16:13:09 -0700456
Simon Glass527298c2015-07-07 20:53:41 -0600457 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
Simon Glass291391b2011-06-13 16:13:09 -0700458
459 /* Enable Tx at SCSRs */
460 reg_val = TX_CFG_ON_;
Simon Glass527298c2015-07-07 20:53:41 -0600461 smsc95xx_write_reg(udev, TX_CFG, reg_val);
Simon Glass291391b2011-06-13 16:13:09 -0700462}
463
464/* Starts the Receive path */
Simon Glass527298c2015-07-07 20:53:41 -0600465static void smsc95xx_start_rx_path(struct usb_device *udev,
466 struct smsc95xx_private *priv)
Simon Glass291391b2011-06-13 16:13:09 -0700467{
Lucas Stache1dbdf92012-08-22 11:04:57 +0000468 priv->mac_cr |= MAC_CR_RXEN_;
Simon Glass527298c2015-07-07 20:53:41 -0600469 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
Simon Glass291391b2011-06-13 16:13:09 -0700470}
471
Simon Glass527298c2015-07-07 20:53:41 -0600472static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
473 struct smsc95xx_private *priv,
474 unsigned char *enetaddr)
Simon Glass291391b2011-06-13 16:13:09 -0700475{
476 int ret;
477 u32 write_buf;
478 u32 read_buf;
479 u32 burst_cap;
480 int timeout;
Simon Glass291391b2011-06-13 16:13:09 -0700481#define TIMEOUT_RESOLUTION 50 /* ms */
482 int link_detected;
483
484 debug("** %s()\n", __func__);
485 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
486
487 write_buf = HW_CFG_LRST_;
Simon Glass527298c2015-07-07 20:53:41 -0600488 ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700489 if (ret < 0)
490 return ret;
491
492 timeout = 0;
493 do {
Simon Glass527298c2015-07-07 20:53:41 -0600494 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700495 if (ret < 0)
496 return ret;
497 udelay(10 * 1000);
498 timeout++;
499 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
500
501 if (timeout >= 100) {
502 debug("timeout waiting for completion of Lite Reset\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600503 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700504 }
505
506 write_buf = PM_CTL_PHY_RST_;
Simon Glass527298c2015-07-07 20:53:41 -0600507 ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700508 if (ret < 0)
509 return ret;
510
511 timeout = 0;
512 do {
Simon Glass527298c2015-07-07 20:53:41 -0600513 ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700514 if (ret < 0)
515 return ret;
516 udelay(10 * 1000);
517 timeout++;
518 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
519 if (timeout >= 100) {
520 debug("timeout waiting for PHY Reset\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600521 return -ETIMEDOUT;
Simon Glass291391b2011-06-13 16:13:09 -0700522 }
Stephen Warrenc9abfbd2016-09-15 12:53:22 -0600523#ifndef CONFIG_DM_ETH
Simon Glass527298c2015-07-07 20:53:41 -0600524 if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
525 0)
Lucas Stache1dbdf92012-08-22 11:04:57 +0000526 priv->have_hwaddr = 1;
Stephen Warrenc9abfbd2016-09-15 12:53:22 -0600527#endif
Lucas Stache1dbdf92012-08-22 11:04:57 +0000528 if (!priv->have_hwaddr) {
Simon Glass291391b2011-06-13 16:13:09 -0700529 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600530 return -EADDRNOTAVAIL;
Simon Glass291391b2011-06-13 16:13:09 -0700531 }
Simon Glass527298c2015-07-07 20:53:41 -0600532 ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
Simon Glass25a9e982015-07-07 20:53:40 -0600533 if (ret < 0)
534 return ret;
Simon Glass291391b2011-06-13 16:13:09 -0700535
Simon Glass291391b2011-06-13 16:13:09 -0700536#ifdef TURBO_MODE
537 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
538 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
Lucas Stache1dbdf92012-08-22 11:04:57 +0000539 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
Simon Glass291391b2011-06-13 16:13:09 -0700540 } else {
541 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
Lucas Stache1dbdf92012-08-22 11:04:57 +0000542 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
Simon Glass291391b2011-06-13 16:13:09 -0700543 }
544#else
545 burst_cap = 0;
Lucas Stache1dbdf92012-08-22 11:04:57 +0000546 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
Simon Glass291391b2011-06-13 16:13:09 -0700547#endif
Lucas Stache1dbdf92012-08-22 11:04:57 +0000548 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
Simon Glass291391b2011-06-13 16:13:09 -0700549
Simon Glass527298c2015-07-07 20:53:41 -0600550 ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
Simon Glass291391b2011-06-13 16:13:09 -0700551 if (ret < 0)
552 return ret;
553
Simon Glass527298c2015-07-07 20:53:41 -0600554 ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700555 if (ret < 0)
556 return ret;
557 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
558
559 read_buf = DEFAULT_BULK_IN_DELAY;
Simon Glass527298c2015-07-07 20:53:41 -0600560 ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700561 if (ret < 0)
562 return ret;
563
Simon Glass527298c2015-07-07 20:53:41 -0600564 ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700565 if (ret < 0)
566 return ret;
567 debug("Read Value from BULK_IN_DLY after writing: "
568 "0x%08x\n", read_buf);
569
Simon Glass527298c2015-07-07 20:53:41 -0600570 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700571 if (ret < 0)
572 return ret;
573 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
574
575#ifdef TURBO_MODE
576 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
577#endif
578 read_buf &= ~HW_CFG_RXDOFF_;
579
580#define NET_IP_ALIGN 0
581 read_buf |= NET_IP_ALIGN << 9;
582
Simon Glass527298c2015-07-07 20:53:41 -0600583 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700584 if (ret < 0)
585 return ret;
586
Simon Glass527298c2015-07-07 20:53:41 -0600587 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700588 if (ret < 0)
589 return ret;
590 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
591
592 write_buf = 0xFFFFFFFF;
Simon Glass527298c2015-07-07 20:53:41 -0600593 ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700594 if (ret < 0)
595 return ret;
596
Simon Glass527298c2015-07-07 20:53:41 -0600597 ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700598 if (ret < 0)
599 return ret;
600 debug("ID_REV = 0x%08x\n", read_buf);
601
Suriyan Ramasami98f686c2013-10-07 20:30:58 -0700602 /* Configure GPIO pins as LED outputs */
603 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
604 LED_GPIO_CFG_FDX_LED;
Simon Glass527298c2015-07-07 20:53:41 -0600605 ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
Suriyan Ramasami98f686c2013-10-07 20:30:58 -0700606 if (ret < 0)
607 return ret;
608 debug("LED_GPIO_CFG set\n");
609
Simon Glass291391b2011-06-13 16:13:09 -0700610 /* Init Tx */
611 write_buf = 0;
Simon Glass527298c2015-07-07 20:53:41 -0600612 ret = smsc95xx_write_reg(udev, FLOW, write_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700613 if (ret < 0)
614 return ret;
615
616 read_buf = AFC_CFG_DEFAULT;
Simon Glass527298c2015-07-07 20:53:41 -0600617 ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700618 if (ret < 0)
619 return ret;
620
Simon Glass527298c2015-07-07 20:53:41 -0600621 ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
Simon Glass291391b2011-06-13 16:13:09 -0700622 if (ret < 0)
623 return ret;
624
625 /* Init Rx. Set Vlan */
626 write_buf = (u32)ETH_P_8021Q;
Simon Glass527298c2015-07-07 20:53:41 -0600627 ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700628 if (ret < 0)
629 return ret;
630
631 /* Disable checksum offload engines */
Simon Glass527298c2015-07-07 20:53:41 -0600632 ret = smsc95xx_set_csums(udev, 0, 0);
Simon Glass291391b2011-06-13 16:13:09 -0700633 if (ret < 0) {
634 debug("Failed to set csum offload: %d\n", ret);
635 return ret;
636 }
Simon Glass527298c2015-07-07 20:53:41 -0600637 smsc95xx_set_multicast(priv);
Simon Glass291391b2011-06-13 16:13:09 -0700638
Simon Glass527298c2015-07-07 20:53:41 -0600639 ret = smsc95xx_phy_initialize(udev, dev);
Simon Glass25a9e982015-07-07 20:53:40 -0600640 if (ret < 0)
641 return ret;
Simon Glass527298c2015-07-07 20:53:41 -0600642 ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700643 if (ret < 0)
644 return ret;
645
646 /* enable PHY interrupts */
647 read_buf |= INT_EP_CTL_PHY_INT_;
648
Simon Glass527298c2015-07-07 20:53:41 -0600649 ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
Simon Glass291391b2011-06-13 16:13:09 -0700650 if (ret < 0)
651 return ret;
652
Simon Glass527298c2015-07-07 20:53:41 -0600653 smsc95xx_start_tx_path(udev, priv);
654 smsc95xx_start_rx_path(udev, priv);
Simon Glass291391b2011-06-13 16:13:09 -0700655
656 timeout = 0;
657 do {
Simon Glass527298c2015-07-07 20:53:41 -0600658 link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
Simon Glass291391b2011-06-13 16:13:09 -0700659 & BMSR_LSTATUS;
660 if (!link_detected) {
661 if (timeout == 0)
662 printf("Waiting for Ethernet connection... ");
663 udelay(TIMEOUT_RESOLUTION * 1000);
664 timeout += TIMEOUT_RESOLUTION;
665 }
666 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
667 if (link_detected) {
668 if (timeout != 0)
669 printf("done.\n");
670 } else {
671 printf("unable to connect.\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600672 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700673 }
674 return 0;
675}
676
Simon Glass527298c2015-07-07 20:53:41 -0600677static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
Simon Glass291391b2011-06-13 16:13:09 -0700678{
Simon Glass291391b2011-06-13 16:13:09 -0700679 int err;
680 int actual_len;
681 u32 tx_cmd_a;
682 u32 tx_cmd_b;
Ilya Yanoke3b31c82012-07-15 04:43:53 +0000683 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
684 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
Simon Glass291391b2011-06-13 16:13:09 -0700685
Prabhakar Kushwahab30dc572015-10-25 13:18:41 +0530686 debug("** %s(), len %d, buf %#x\n", __func__, length,
687 (unsigned int)(ulong)msg);
Simon Glass291391b2011-06-13 16:13:09 -0700688 if (length > PKTSIZE)
Simon Glass25a9e982015-07-07 20:53:40 -0600689 return -ENOSPC;
Simon Glass291391b2011-06-13 16:13:09 -0700690
691 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
692 tx_cmd_b = (u32)length;
693 cpu_to_le32s(&tx_cmd_a);
694 cpu_to_le32s(&tx_cmd_b);
695
696 /* prepend cmd_a and cmd_b */
697 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
698 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
699 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
700 length);
701 err = usb_bulk_msg(dev->pusb_dev,
702 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
703 (void *)msg,
704 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
705 &actual_len,
706 USB_BULK_SEND_TIMEOUT);
707 debug("Tx: len = %u, actual = %u, err = %d\n",
Prabhakar Kushwahab30dc572015-10-25 13:18:41 +0530708 (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)),
709 (unsigned int)actual_len, err);
Simon Glass527298c2015-07-07 20:53:41 -0600710
Simon Glass291391b2011-06-13 16:13:09 -0700711 return err;
712}
713
Simon Glass0990fcb2015-07-07 20:53:42 -0600714#ifndef CONFIG_DM_ETH
Simon Glass527298c2015-07-07 20:53:41 -0600715/*
716 * Smsc95xx callbacks
717 */
718static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
719{
720 struct ueth_data *dev = (struct ueth_data *)eth->priv;
721 struct usb_device *udev = dev->pusb_dev;
722 struct smsc95xx_private *priv =
723 (struct smsc95xx_private *)dev->dev_priv;
724
725 return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
726}
727
728static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
729{
730 struct ueth_data *dev = (struct ueth_data *)eth->priv;
731
732 return smsc95xx_send_common(dev, packet, length);
733}
734
Simon Glass291391b2011-06-13 16:13:09 -0700735static int smsc95xx_recv(struct eth_device *eth)
736{
737 struct ueth_data *dev = (struct ueth_data *)eth->priv;
Simon Glassd62a1dc2015-07-07 20:53:39 -0600738 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
Simon Glass291391b2011-06-13 16:13:09 -0700739 unsigned char *buf_ptr;
740 int err;
741 int actual_len;
742 u32 packet_len;
743 int cur_buf_align;
744
745 debug("** %s()\n", __func__);
746 err = usb_bulk_msg(dev->pusb_dev,
Simon Glass527298c2015-07-07 20:53:41 -0600747 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
748 (void *)recv_buf, RX_URB_SIZE, &actual_len,
749 USB_BULK_RECV_TIMEOUT);
Simon Glassd62a1dc2015-07-07 20:53:39 -0600750 debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
Simon Glass291391b2011-06-13 16:13:09 -0700751 actual_len, err);
752 if (err != 0) {
753 debug("Rx: failed to receive\n");
Simon Glass527298c2015-07-07 20:53:41 -0600754 return -err;
Simon Glass291391b2011-06-13 16:13:09 -0700755 }
Simon Glassd62a1dc2015-07-07 20:53:39 -0600756 if (actual_len > RX_URB_SIZE) {
Simon Glass291391b2011-06-13 16:13:09 -0700757 debug("Rx: received too many bytes %d\n", actual_len);
Simon Glass25a9e982015-07-07 20:53:40 -0600758 return -ENOSPC;
Simon Glass291391b2011-06-13 16:13:09 -0700759 }
760
761 buf_ptr = recv_buf;
762 while (actual_len > 0) {
763 /*
764 * 1st 4 bytes contain the length of the actual data plus error
765 * info. Extract data length.
766 */
767 if (actual_len < sizeof(packet_len)) {
768 debug("Rx: incomplete packet length\n");
Simon Glass25a9e982015-07-07 20:53:40 -0600769 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700770 }
771 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
772 le32_to_cpus(&packet_len);
773 if (packet_len & RX_STS_ES_) {
774 debug("Rx: Error header=%#x", packet_len);
Simon Glass25a9e982015-07-07 20:53:40 -0600775 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700776 }
777 packet_len = ((packet_len & RX_STS_FL_) >> 16);
778
779 if (packet_len > actual_len - sizeof(packet_len)) {
780 debug("Rx: too large packet: %d\n", packet_len);
Simon Glass25a9e982015-07-07 20:53:40 -0600781 return -EIO;
Simon Glass291391b2011-06-13 16:13:09 -0700782 }
783
784 /* Notify net stack */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500785 net_process_received_packet(buf_ptr + sizeof(packet_len),
786 packet_len - 4);
Simon Glass291391b2011-06-13 16:13:09 -0700787
788 /* Adjust for next iteration */
789 actual_len -= sizeof(packet_len) + packet_len;
790 buf_ptr += sizeof(packet_len) + packet_len;
Prabhakar Kushwahab30dc572015-10-25 13:18:41 +0530791 cur_buf_align = (ulong)buf_ptr - (ulong)recv_buf;
Simon Glass291391b2011-06-13 16:13:09 -0700792
793 if (cur_buf_align & 0x03) {
794 int align = 4 - (cur_buf_align & 0x03);
795
796 actual_len -= align;
797 buf_ptr += align;
798 }
799 }
800 return err;
801}
802
803static void smsc95xx_halt(struct eth_device *eth)
804{
805 debug("** %s()\n", __func__);
806}
807
Simon Glass527298c2015-07-07 20:53:41 -0600808static int smsc95xx_write_hwaddr(struct eth_device *eth)
809{
810 struct ueth_data *dev = eth->priv;
811 struct usb_device *udev = dev->pusb_dev;
812 struct smsc95xx_private *priv = dev->dev_priv;
813
814 return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
815}
816
Simon Glass291391b2011-06-13 16:13:09 -0700817/*
818 * SMSC probing functions
819 */
820void smsc95xx_eth_before_probe(void)
821{
822 curr_eth_dev = 0;
823}
824
825struct smsc95xx_dongle {
826 unsigned short vendor;
827 unsigned short product;
828};
829
830static const struct smsc95xx_dongle smsc95xx_dongles[] = {
831 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
832 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
Lubomir Popove7dcece2013-04-01 04:50:55 +0000833 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
Stefan Roese2eb60902013-07-03 18:34:54 +0200834 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
Ilya Ledvich08ebd462014-03-12 10:36:31 +0200835 { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
Simon Glass291391b2011-06-13 16:13:09 -0700836 { 0x0000, 0x0000 } /* END - Do not remove */
837};
838
839/* Probe to see if a new device is actually an SMSC device */
840int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
841 struct ueth_data *ss)
842{
843 struct usb_interface *iface;
844 struct usb_interface_descriptor *iface_desc;
845 int i;
846
847 /* let's examine the device now */
848 iface = &dev->config.if_desc[ifnum];
849 iface_desc = &dev->config.if_desc[ifnum].desc;
850
851 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
852 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
853 dev->descriptor.idProduct == smsc95xx_dongles[i].product)
854 /* Found a supported dongle */
855 break;
856 }
857 if (smsc95xx_dongles[i].vendor == 0)
858 return 0;
859
860 /* At this point, we know we've got a live one */
861 debug("\n\nUSB Ethernet device detected\n");
862 memset(ss, '\0', sizeof(struct ueth_data));
863
864 /* Initialize the ueth_data structure with some useful info */
865 ss->ifnum = ifnum;
866 ss->pusb_dev = dev;
867 ss->subclass = iface_desc->bInterfaceSubClass;
868 ss->protocol = iface_desc->bInterfaceProtocol;
869
870 /*
871 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
872 * We will ignore any others.
873 */
874 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
875 /* is it an BULK endpoint? */
876 if ((iface->ep_desc[i].bmAttributes &
877 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
878 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
879 ss->ep_in =
880 iface->ep_desc[i].bEndpointAddress &
881 USB_ENDPOINT_NUMBER_MASK;
882 else
883 ss->ep_out =
884 iface->ep_desc[i].bEndpointAddress &
885 USB_ENDPOINT_NUMBER_MASK;
886 }
887
888 /* is it an interrupt endpoint? */
889 if ((iface->ep_desc[i].bmAttributes &
890 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
891 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
892 USB_ENDPOINT_NUMBER_MASK;
893 ss->irqinterval = iface->ep_desc[i].bInterval;
894 }
895 }
896 debug("Endpoints In %d Out %d Int %d\n",
897 ss->ep_in, ss->ep_out, ss->ep_int);
898
899 /* Do some basic sanity checks, and bail if we find a problem */
900 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
901 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
902 debug("Problems with device\n");
903 return 0;
904 }
905 dev->privptr = (void *)ss;
Lucas Stache1dbdf92012-08-22 11:04:57 +0000906
907 /* alloc driver private */
908 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
909 if (!ss->dev_priv)
910 return 0;
911
Simon Glass291391b2011-06-13 16:13:09 -0700912 return 1;
913}
914
915int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
916 struct eth_device *eth)
917{
918 debug("** %s()\n", __func__);
919 if (!eth) {
920 debug("%s: missing parameter.\n", __func__);
921 return 0;
922 }
923 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
924 eth->init = smsc95xx_init;
925 eth->send = smsc95xx_send;
926 eth->recv = smsc95xx_recv;
927 eth->halt = smsc95xx_halt;
928 eth->write_hwaddr = smsc95xx_write_hwaddr;
929 eth->priv = ss;
930 return 1;
931}
Simon Glass0990fcb2015-07-07 20:53:42 -0600932#endif /* !CONFIG_DM_ETH */
933
934#ifdef CONFIG_DM_ETH
935static int smsc95xx_eth_start(struct udevice *dev)
936{
Simon Glassbcbe3d12015-09-28 23:32:01 -0600937 struct usb_device *udev = dev_get_parent_priv(dev);
Simon Glass0990fcb2015-07-07 20:53:42 -0600938 struct smsc95xx_private *priv = dev_get_priv(dev);
939 struct eth_pdata *pdata = dev_get_platdata(dev);
940
941 /* Driver-model Ethernet ensures we have this */
942 priv->have_hwaddr = 1;
943
944 return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
945}
946
947void smsc95xx_eth_stop(struct udevice *dev)
948{
949 debug("** %s()\n", __func__);
950}
951
952int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
953{
954 struct smsc95xx_private *priv = dev_get_priv(dev);
955
956 return smsc95xx_send_common(&priv->ueth, packet, length);
957}
958
959int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
960{
961 struct smsc95xx_private *priv = dev_get_priv(dev);
962 struct ueth_data *ueth = &priv->ueth;
963 uint8_t *ptr;
964 int ret, len;
965 u32 packet_len;
966
967 len = usb_ether_get_rx_bytes(ueth, &ptr);
968 debug("%s: first try, len=%d\n", __func__, len);
969 if (!len) {
970 if (!(flags & ETH_RECV_CHECK_DEVICE))
971 return -EAGAIN;
972 ret = usb_ether_receive(ueth, RX_URB_SIZE);
973 if (ret == -EAGAIN)
974 return ret;
975
976 len = usb_ether_get_rx_bytes(ueth, &ptr);
977 debug("%s: second try, len=%d\n", __func__, len);
978 }
979
980 /*
981 * 1st 4 bytes contain the length of the actual data plus error info.
982 * Extract data length.
983 */
984 if (len < sizeof(packet_len)) {
985 debug("Rx: incomplete packet length\n");
986 goto err;
987 }
988 memcpy(&packet_len, ptr, sizeof(packet_len));
989 le32_to_cpus(&packet_len);
990 if (packet_len & RX_STS_ES_) {
991 debug("Rx: Error header=%#x", packet_len);
992 goto err;
993 }
994 packet_len = ((packet_len & RX_STS_FL_) >> 16);
995
996 if (packet_len > len - sizeof(packet_len)) {
997 debug("Rx: too large packet: %d\n", packet_len);
998 goto err;
999 }
1000
1001 *packetp = ptr + sizeof(packet_len);
Simon Glass20b429b2017-04-05 16:23:28 -06001002 return packet_len - 4;
Simon Glass0990fcb2015-07-07 20:53:42 -06001003
1004err:
1005 usb_ether_advance_rxbuf(ueth, -1);
1006 return -EINVAL;
1007}
1008
1009static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1010{
1011 struct smsc95xx_private *priv = dev_get_priv(dev);
1012
Simon Glass20b429b2017-04-05 16:23:28 -06001013 packet_len = ALIGN(packet_len + sizeof(u32), 4);
Simon Glass0990fcb2015-07-07 20:53:42 -06001014 usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
1015
1016 return 0;
1017}
1018
1019int smsc95xx_write_hwaddr(struct udevice *dev)
1020{
Simon Glassbcbe3d12015-09-28 23:32:01 -06001021 struct usb_device *udev = dev_get_parent_priv(dev);
Simon Glass0990fcb2015-07-07 20:53:42 -06001022 struct eth_pdata *pdata = dev_get_platdata(dev);
1023 struct smsc95xx_private *priv = dev_get_priv(dev);
1024
1025 return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
1026}
1027
Stephen Warrenc9abfbd2016-09-15 12:53:22 -06001028int smsc95xx_read_rom_hwaddr(struct udevice *dev)
1029{
1030 struct usb_device *udev = dev_get_parent_priv(dev);
1031 struct eth_pdata *pdata = dev_get_platdata(dev);
1032 int ret;
1033
1034 ret = smsc95xx_init_mac_address(pdata->enetaddr, udev);
1035 if (ret)
1036 memset(pdata->enetaddr, 0, 6);
1037
1038 return 0;
1039}
1040
Simon Glass0990fcb2015-07-07 20:53:42 -06001041static int smsc95xx_eth_probe(struct udevice *dev)
1042{
1043 struct smsc95xx_private *priv = dev_get_priv(dev);
1044 struct ueth_data *ueth = &priv->ueth;
1045
1046 return usb_ether_register(dev, ueth, RX_URB_SIZE);
1047}
1048
1049static const struct eth_ops smsc95xx_eth_ops = {
1050 .start = smsc95xx_eth_start,
1051 .send = smsc95xx_eth_send,
1052 .recv = smsc95xx_eth_recv,
1053 .free_pkt = smsc95xx_free_pkt,
1054 .stop = smsc95xx_eth_stop,
1055 .write_hwaddr = smsc95xx_write_hwaddr,
Stephen Warrenc9abfbd2016-09-15 12:53:22 -06001056 .read_rom_hwaddr = smsc95xx_read_rom_hwaddr,
Simon Glass0990fcb2015-07-07 20:53:42 -06001057};
1058
1059U_BOOT_DRIVER(smsc95xx_eth) = {
1060 .name = "smsc95xx_eth",
1061 .id = UCLASS_ETH,
1062 .probe = smsc95xx_eth_probe,
1063 .ops = &smsc95xx_eth_ops,
1064 .priv_auto_alloc_size = sizeof(struct smsc95xx_private),
1065 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1066};
1067
1068static const struct usb_device_id smsc95xx_eth_id_table[] = {
1069 { USB_DEVICE(0x05ac, 0x1402) },
1070 { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */
1071 { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */
1072 { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */
1073 { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */
1074 { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */
1075 { } /* Terminating entry */
1076};
1077
1078U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);
1079#endif