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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / f7d1572bf51619554f278cb543ef0445baa3a1f8 / . / board / uc100 / uc100.c
blob: 55977906d8ca8b479fd59e5ebe49294e699e5837 [file] [log] [blame]
wdenkf7d15722004-12-18 22:35:43 +0000[diff] [blame^]1/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#if 0
25#define DEBUG
26#endif
27
28#include <common.h>
29#include <mpc8xx.h>
30#include <i2c.h>
31
32
33/*********************************************************************/
34/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */
35/*********************************************************************/
36const uint sdram_init_upm_table[] = {
37 /* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
38 /* NOP - Precharge - AutoRefr - NOP - NOP */
39 /* NOP - AutoRefr - NOP */
40 /* NOP - NOP - LoadModeR - NOP - Active */
41 /* Position of Single Read */
42 0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
43 0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,
44
45 /* Burst Read. (offset 8 in UPMA RAM) */
46 /* Cycle lent for Initialisation WV */
47 0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
48 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
49 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
50
51 /* Single Write. (offset 18 in UPMA RAM) */
52 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
53 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
54
55 /* Burst Write. (offset 20 in UPMA RAM) */
56 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
57 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
58 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
59
60 /* Refresh (offset 30 in UPMA RAM) */
61 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
62 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
63 0xFFFFFFFF, 0xFFFFFFFF,
64
65 /* Exception. (offset 3c in UPMA RAM) */
66 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
67};
68
69/*********************************************************************/
70/* UPMA initilization table. */
71/*********************************************************************/
72const uint sdram_upm_table[] = {
73 /* single read. (offset 0 in UPMA RAM) */
74 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
75 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x05-0x07 new WV */
76
77 /* Burst Read. (offset 8 in UPMA RAM) */
78 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
79 0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
80 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
81
82 /* Single Write. (offset 18 in UPMA RAM) */
83 0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
84 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
85
86 /* Burst Write. (offset 20 in UPMA RAM) */
87 0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
88 0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
89 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
90
91 /* Refresh (offset 30 in UPMA RAM) */
92 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
93 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
94 0xFFFFFFFF, 0xFFFFFFFF,
95
96 /* Exception. (offset 3c in UPMA RAM) */
97 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
98};
99
100/*********************************************************************/
101/* UPMB initilization table. */
102/*********************************************************************/
103const uint mpm_upm_table[] = {
104 /* single read. (offset 0 in upm RAM) */
105 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
106 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
107
108 /* burst read. (Offset 8 in upm RAM) */
109 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
110 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
111 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
112 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
113
114 /* single write. (Offset 0x18 in upm RAM) */
115 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
116 0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,
117
118 /* burst write. (Offset 0x20 in upm RAM) */
119 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
120 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
121 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
122 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
123
124 /* Refresh cycle, offset 0x30 */
125 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
126 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
127 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
128
129 /* Exception, 0ffset 0x3C */
130 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
131};
132
133
134int board_switch(void)
135{
136 volatile pcmconf8xx_t *pcmp;
137
138 pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
139
140 return ((pcmp->pcmc_pipr >> 24) & 0xf);
141}
142
143
144/*
145 * Check Board Identity:
146 */
147int checkboard (void)
148{
149 unsigned char str[64];
150 int i = getenv_r ("serial#", str, sizeof(str));
151
152 puts ("Board: ");
153
154 if (i == -1) {
155 puts ("### No HW ID - assuming UC100");
156 } else {
157 puts(str);
158 }
159
160 printf (" (SWITCH=%1X)\n", board_switch());
161
162 return 0;
163}
164
165
166/*
167 * Initialize SDRAM
168 */
169long int initdram (int board_type)
170{
171 volatile immap_t *immap = (immap_t *) CFG_IMMR;
172 volatile memctl8xx_t *memctl = &immap->im_memctl;
173
174 /*---------------------------------------------------------------------*/
175 /* Initialize the UPMA/UPMB registers with the appropriate table. */
176 /*---------------------------------------------------------------------*/
177 upmconfig (UPMA, (uint *) sdram_init_upm_table,
178 sizeof (sdram_init_upm_table) / sizeof (uint));
179 upmconfig (UPMB, (uint *) mpm_upm_table,
180 sizeof (mpm_upm_table) / sizeof (uint));
181
182 /*---------------------------------------------------------------------*/
183 /* Memory Periodic Timer Prescaler: divide by 16 */
184 /*---------------------------------------------------------------------*/
185 memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
186
187 memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
188 memctl->memc_mbmr = CFG_MBMR_VAL;
189
190 /*---------------------------------------------------------------------*/
191 /* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */
192 /* for SDRAM */
193 /* */
194 /* NOTE: The refresh rate in MAMR reg is set according to the lowest */
195 /* clock rate (16.67MHz) to allow proper operation for all ADS */
196 /* clock frequencies. */
197 /*---------------------------------------------------------------------*/
198 memctl->memc_or1 = CFG_OR1_PRELIM;
199 memctl->memc_br1 = CFG_BR1_PRELIM;
200
201 /*-------------------------------------------------------------------*/
202 /* Wait at least 200 usec for DRAM to stabilize, this magic number */
203 /* obtained from the init code. */
204 /*-------------------------------------------------------------------*/
205 udelay(200);
206
207 memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;
208
209 memctl->memc_br1 = CFG_BR1_PRELIM;
210 memctl->memc_or1 = CFG_OR1_PRELIM;
211
212 /*---------------------------------------------------------------------*/
213 /* run MRS command in location 5-8 of UPMB. */
214 /*---------------------------------------------------------------------*/
215 memctl->memc_mar = 0x88;
216 /* RUN UPMA on CS1 1-time from UPMA addr 0x05 */
217
218 memctl->memc_mcr = 0x80002100;
219 /* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */
220
221 udelay(200);
222
223 /*---------------------------------------------------------------------*/
224 /* Initialisation for normal access WV */
225 /*---------------------------------------------------------------------*/
226
227 /*---------------------------------------------------------------------*/
228 /* Initialize the UPMA register with the appropriate table. */
229 /*---------------------------------------------------------------------*/
230 upmconfig (UPMA, (uint *) sdram_upm_table,
231 sizeof (sdram_upm_table) / sizeof (uint));
232
233 /*---------------------------------------------------------------------*/
234 /* rerstore MBMR value (4-beat refresh burst.) */
235 /*---------------------------------------------------------------------*/
236 memctl->memc_mamr = CFG_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
237
238 udelay(200);
239
240 return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
241}
242
243
244int misc_init_r (void)
245{
246 uchar val;
247
248 /*
249 * Make sure that RTC has clock output enabled (triggers watchdog!)
250 */
251 val = i2c_reg_read (CFG_I2C_RTC_ADDR, 0x0D);
252 val |= 0x80;
253 i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val);
254
255 return 0;
256}
257
258
259#ifdef CONFIG_POST
260/*
261 * Returns 1 if keys pressed to start the power-on long-running tests
262 * Called from board_init_f().
263 */
264int post_hotkeys_pressed (void)
265{
266 return 0; /* No hotkeys supported */
267}
268#endif