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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese10e8bf82014-11-07 12:37:49 +01002/*
3 * Copyright (C) 2012
4 * Altera Corporation <www.altera.com>
Stefan Roese10e8bf82014-11-07 12:37:49 +01005 */
6
7#include <common.h>
Simon Goldschmidt64c7c8c2019-11-20 22:27:31 +01008#include <clk.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06009#include <log.h>
Vignesh Raghavendra0f247842019-12-05 15:46:06 +053010#include <asm-generic/io.h>
Stefan Roese10e8bf82014-11-07 12:37:49 +010011#include <dm.h>
12#include <fdtdec.h>
13#include <malloc.h>
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +010014#include <reset.h>
Stefan Roese10e8bf82014-11-07 12:37:49 +010015#include <spi.h>
Vignesh Raghavendrad6407722020-01-27 10:36:39 +053016#include <spi-mem.h>
Simon Glass336d4612020-02-03 07:36:16 -070017#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -070018#include <linux/err.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090019#include <linux/errno.h>
Vignesh Raghavendraffab2122020-01-27 10:36:40 +053020#include <linux/sizes.h>
T Karthik Reddy248fe9f2022-05-12 04:05:34 -060021#include <zynqmp_firmware.h>
Stefan Roese10e8bf82014-11-07 12:37:49 +010022#include "cadence_qspi.h"
T Karthik Reddy248fe9f2022-05-12 04:05:34 -060023#include <dt-bindings/power/xlnx-versal-power.h>
Stefan Roese10e8bf82014-11-07 12:37:49 +010024
Pratyush Yadava6903aa2021-06-26 00:47:08 +053025#define NSEC_PER_SEC 1000000000L
26
Stefan Roese10e8bf82014-11-07 12:37:49 +010027#define CQSPI_STIG_READ 0
28#define CQSPI_STIG_WRITE 1
Vignesh Raghavendraffab2122020-01-27 10:36:40 +053029#define CQSPI_READ 2
30#define CQSPI_WRITE 3
Stefan Roese10e8bf82014-11-07 12:37:49 +010031
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -060032__weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
T Karthik Reddycf553bf2022-05-12 04:05:32 -060033 const struct spi_mem_op *op)
34{
35 return 0;
36}
37
T Karthik Reddybf8dae52022-05-12 04:05:33 -060038__weak int cadence_qspi_versal_flash_reset(struct udevice *dev)
39{
40 return 0;
41}
42
Stefan Roese10e8bf82014-11-07 12:37:49 +010043static int cadence_spi_write_speed(struct udevice *bus, uint hz)
44{
Stefan Roese10e8bf82014-11-07 12:37:49 +010045 struct cadence_spi_priv *priv = dev_get_priv(bus);
46
47 cadence_qspi_apb_config_baudrate_div(priv->regbase,
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -060048 priv->ref_clk_hz, hz);
Stefan Roese10e8bf82014-11-07 12:37:49 +010049
50 /* Reconfigure delay timing if speed is changed. */
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -060051 cadence_qspi_apb_delay(priv->regbase, priv->ref_clk_hz, hz,
52 priv->tshsl_ns, priv->tsd2d_ns,
53 priv->tchsh_ns, priv->tslch_ns);
Stefan Roese10e8bf82014-11-07 12:37:49 +010054
55 return 0;
56}
57
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -060058static int cadence_spi_read_id(struct cadence_spi_priv *priv, u8 len,
Pratyush Yadav38b08522021-06-26 00:47:09 +053059 u8 *idcode)
Vignesh Raghavendrad6407722020-01-27 10:36:39 +053060{
Ashok Reddy Somad0003b52022-08-24 05:38:46 -060061 int err;
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -060062
Vignesh Raghavendrad6407722020-01-27 10:36:39 +053063 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
64 SPI_MEM_OP_NO_ADDR,
65 SPI_MEM_OP_NO_DUMMY,
66 SPI_MEM_OP_DATA_IN(len, idcode, 1));
67
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -060068 err = cadence_qspi_apb_command_read_setup(priv, &op);
Ashok Reddy Somad0003b52022-08-24 05:38:46 -060069 if (!err)
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -060070 err = cadence_qspi_apb_command_read(priv, &op);
Ashok Reddy Somad0003b52022-08-24 05:38:46 -060071
72 return err;
Vignesh Raghavendrad6407722020-01-27 10:36:39 +053073}
74
Stefan Roese10e8bf82014-11-07 12:37:49 +010075/* Calibration sequence to determine the read data capture delay register */
Chin Liang See98fbd712015-10-17 08:31:55 -050076static int spi_calibration(struct udevice *bus, uint hz)
Stefan Roese10e8bf82014-11-07 12:37:49 +010077{
Stefan Roese10e8bf82014-11-07 12:37:49 +010078 struct cadence_spi_priv *priv = dev_get_priv(bus);
79 void *base = priv->regbase;
Stefan Roese10e8bf82014-11-07 12:37:49 +010080 unsigned int idcode = 0, temp = 0;
81 int err = 0, i, range_lo = -1, range_hi = -1;
82
83 /* start with slowest clock (1 MHz) */
84 cadence_spi_write_speed(bus, 1000000);
85
86 /* configure the read data capture delay register to 0 */
87 cadence_qspi_apb_readdata_capture(base, 1, 0);
88
89 /* Enable QSPI */
90 cadence_qspi_apb_controller_enable(base);
91
92 /* read the ID which will be our golden value */
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -060093 err = cadence_spi_read_id(priv, 3, (u8 *)&idcode);
Stefan Roese10e8bf82014-11-07 12:37:49 +010094 if (err) {
95 puts("SF: Calibration failed (read)\n");
96 return err;
97 }
98
99 /* use back the intended clock and find low range */
Chin Liang See98fbd712015-10-17 08:31:55 -0500100 cadence_spi_write_speed(bus, hz);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100101 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
102 /* Disable QSPI */
103 cadence_qspi_apb_controller_disable(base);
104
105 /* reconfigure the read data capture delay register */
106 cadence_qspi_apb_readdata_capture(base, 1, i);
107
108 /* Enable back QSPI */
109 cadence_qspi_apb_controller_enable(base);
110
111 /* issue a RDID to get the ID value */
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600112 err = cadence_spi_read_id(priv, 3, (u8 *)&temp);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100113 if (err) {
114 puts("SF: Calibration failed (read)\n");
115 return err;
116 }
117
118 /* search for range lo */
119 if (range_lo == -1 && temp == idcode) {
120 range_lo = i;
121 continue;
122 }
123
124 /* search for range hi */
125 if (range_lo != -1 && temp != idcode) {
126 range_hi = i - 1;
127 break;
128 }
129 range_hi = i;
130 }
131
132 if (range_lo == -1) {
133 puts("SF: Calibration failed (low range)\n");
134 return err;
135 }
136
137 /* Disable QSPI for subsequent initialization */
138 cadence_qspi_apb_controller_disable(base);
139
140 /* configure the final value for read data capture delay register */
141 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
142 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
143 (range_hi + range_lo) / 2, range_lo, range_hi);
144
145 /* just to ensure we do once only when speed or chip select change */
Chin Liang See98fbd712015-10-17 08:31:55 -0500146 priv->qspi_calibrated_hz = hz;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100147 priv->qspi_calibrated_cs = spi_chip_select(bus);
148
149 return 0;
150}
151
152static int cadence_spi_set_speed(struct udevice *bus, uint hz)
153{
Stefan Roese10e8bf82014-11-07 12:37:49 +0100154 struct cadence_spi_priv *priv = dev_get_priv(bus);
155 int err;
156
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600157 if (!hz || hz > priv->max_hz)
158 hz = priv->max_hz;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100159 /* Disable QSPI */
160 cadence_qspi_apb_controller_disable(priv->regbase);
161
Chin Liang See98fbd712015-10-17 08:31:55 -0500162 /*
Pratyush Yadavbd8c8dc2021-06-26 00:47:07 +0530163 * If the device tree already provides a read delay value, use that
164 * instead of calibrating.
Chin Liang See98fbd712015-10-17 08:31:55 -0500165 */
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600166 if (priv->read_delay >= 0) {
Pratyush Yadavbd8c8dc2021-06-26 00:47:07 +0530167 cadence_spi_write_speed(bus, hz);
168 cadence_qspi_apb_readdata_capture(priv->regbase, 1,
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600169 priv->read_delay);
Pratyush Yadavbd8c8dc2021-06-26 00:47:07 +0530170 } else if (priv->previous_hz != hz ||
171 priv->qspi_calibrated_hz != hz ||
172 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
173 /*
174 * Calibration required for different current SCLK speed,
175 * requested SCLK speed or chip select
176 */
Chin Liang See98fbd712015-10-17 08:31:55 -0500177 err = spi_calibration(bus, hz);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100178 if (err)
179 return err;
Chin Liang See98fbd712015-10-17 08:31:55 -0500180
181 /* prevent calibration run when same as previous request */
182 priv->previous_hz = hz;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100183 }
184
185 /* Enable QSPI */
186 cadence_qspi_apb_controller_enable(priv->regbase);
187
188 debug("%s: speed=%d\n", __func__, hz);
189
190 return 0;
191}
192
193static int cadence_spi_probe(struct udevice *bus)
194{
Simon Glass0fd3d912020-12-22 19:30:28 -0700195 struct cadence_spi_plat *plat = dev_get_plat(bus);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100196 struct cadence_spi_priv *priv = dev_get_priv(bus);
Pratyush Yadav0a9c2872020-02-24 12:40:51 +0530197 struct clk clk;
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +0100198 int ret;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100199
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600200 priv->regbase = plat->regbase;
201 priv->ahbbase = plat->ahbbase;
202 priv->is_dma = plat->is_dma;
203 priv->is_decoded_cs = plat->is_decoded_cs;
204 priv->fifo_depth = plat->fifo_depth;
205 priv->fifo_width = plat->fifo_width;
206 priv->trigger_address = plat->trigger_address;
207 priv->read_delay = plat->read_delay;
208 priv->ahbsize = plat->ahbsize;
209 priv->max_hz = plat->max_hz;
210
211 priv->page_size = plat->page_size;
212 priv->block_size = plat->block_size;
213 priv->tshsl_ns = plat->tshsl_ns;
214 priv->tsd2d_ns = plat->tsd2d_ns;
215 priv->tchsh_ns = plat->tchsh_ns;
216 priv->tslch_ns = plat->tslch_ns;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100217
T Karthik Reddy248fe9f2022-05-12 04:05:34 -0600218 if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE))
219 xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
220 ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
221 ZYNQMP_PM_REQUEST_ACK_NO, NULL);
222
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600223 if (priv->ref_clk_hz == 0) {
Pratyush Yadav0a9c2872020-02-24 12:40:51 +0530224 ret = clk_get_by_index(bus, 0, &clk);
225 if (ret) {
Tom Rini55b3ba42022-03-30 18:07:23 -0400226#ifdef CONFIG_HAS_CQSPI_REF_CLK
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600227 priv->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
Tom Rini55b3ba42022-03-30 18:07:23 -0400228#elif defined(CONFIG_ARCH_SOCFPGA)
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600229 priv->ref_clk_hz = cm_get_qspi_controller_clk_hz();
Pratyush Yadav0a9c2872020-02-24 12:40:51 +0530230#else
231 return ret;
232#endif
233 } else {
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600234 priv->ref_clk_hz = clk_get_rate(&clk);
Pratyush Yadav0a9c2872020-02-24 12:40:51 +0530235 clk_free(&clk);
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600236 if (IS_ERR_VALUE(priv->ref_clk_hz))
237 return priv->ref_clk_hz;
Pratyush Yadav0a9c2872020-02-24 12:40:51 +0530238 }
239 }
240
Christian Gmeinere1456062022-02-22 17:23:25 +0100241 priv->resets = devm_reset_bulk_get_optional(bus);
242 if (priv->resets)
243 reset_deassert_bulk(priv->resets);
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +0100244
Stefan Roese10e8bf82014-11-07 12:37:49 +0100245 if (!priv->qspi_is_init) {
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600246 cadence_qspi_apb_controller_init(priv);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100247 priv->qspi_is_init = 1;
248 }
249
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600250 priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
Pratyush Yadava6903aa2021-06-26 00:47:08 +0530251
T Karthik Reddybf8dae52022-05-12 04:05:33 -0600252 if (CONFIG_IS_ENABLED(ARCH_VERSAL)) {
253 /* Versal platform uses spi calibration to set read delay */
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600254 if (priv->read_delay >= 0)
255 priv->read_delay = -1;
T Karthik Reddybf8dae52022-05-12 04:05:33 -0600256 /* Reset ospi flash device */
257 ret = cadence_qspi_versal_flash_reset(bus);
258 if (ret)
259 return ret;
260 }
261
Stefan Roese10e8bf82014-11-07 12:37:49 +0100262 return 0;
263}
264
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +0100265static int cadence_spi_remove(struct udevice *dev)
266{
267 struct cadence_spi_priv *priv = dev_get_priv(dev);
Christian Gmeinere1456062022-02-22 17:23:25 +0100268 int ret = 0;
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +0100269
Christian Gmeinere1456062022-02-22 17:23:25 +0100270 if (priv->resets)
271 ret = reset_release_bulk(priv->resets);
272
273 return ret;
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +0100274}
275
Stefan Roese10e8bf82014-11-07 12:37:49 +0100276static int cadence_spi_set_mode(struct udevice *bus, uint mode)
277{
278 struct cadence_spi_priv *priv = dev_get_priv(bus);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100279
280 /* Disable QSPI */
281 cadence_qspi_apb_controller_disable(priv->regbase);
282
283 /* Set SPI mode */
Phil Edworthy7d403f22016-11-29 12:58:31 +0000284 cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100285
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530286 /* Enable Direct Access Controller */
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600287 if (priv->use_dac_mode)
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530288 cadence_qspi_apb_dac_mode_enable(priv->regbase);
289
Stefan Roese10e8bf82014-11-07 12:37:49 +0100290 /* Enable QSPI */
291 cadence_qspi_apb_controller_enable(priv->regbase);
292
293 return 0;
294}
295
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530296static int cadence_spi_mem_exec_op(struct spi_slave *spi,
297 const struct spi_mem_op *op)
Stefan Roese10e8bf82014-11-07 12:37:49 +0100298{
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530299 struct udevice *bus = spi->dev->parent;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100300 struct cadence_spi_priv *priv = dev_get_priv(bus);
301 void *base = priv->regbase;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100302 int err = 0;
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530303 u32 mode;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100304
305 /* Set Chip select */
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530306 cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600307 priv->is_decoded_cs);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100308
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530309 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
310 if (!op->addr.nbytes)
311 mode = CQSPI_STIG_READ;
312 else
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530313 mode = CQSPI_READ;
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530314 } else {
315 if (!op->addr.nbytes || !op->data.buf.out)
316 mode = CQSPI_STIG_WRITE;
317 else
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530318 mode = CQSPI_WRITE;
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530319 }
Stefan Roese10e8bf82014-11-07 12:37:49 +0100320
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530321 switch (mode) {
322 case CQSPI_STIG_READ:
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600323 err = cadence_qspi_apb_command_read_setup(priv, op);
Pratyush Yadav38b08522021-06-26 00:47:09 +0530324 if (!err)
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600325 err = cadence_qspi_apb_command_read(priv, op);
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530326 break;
327 case CQSPI_STIG_WRITE:
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600328 err = cadence_qspi_apb_command_write_setup(priv, op);
Pratyush Yadav38b08522021-06-26 00:47:09 +0530329 if (!err)
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600330 err = cadence_qspi_apb_command_write(priv, op);
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530331 break;
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530332 case CQSPI_READ:
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600333 err = cadence_qspi_apb_read_setup(priv, op);
T Karthik Reddycf553bf2022-05-12 04:05:32 -0600334 if (!err) {
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600335 if (priv->is_dma)
336 err = cadence_qspi_apb_dma_read(priv, op);
T Karthik Reddycf553bf2022-05-12 04:05:32 -0600337 else
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600338 err = cadence_qspi_apb_read_execute(priv, op);
T Karthik Reddycf553bf2022-05-12 04:05:32 -0600339 }
Stefan Roese10e8bf82014-11-07 12:37:49 +0100340 break;
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530341 case CQSPI_WRITE:
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600342 err = cadence_qspi_apb_write_setup(priv, op);
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530343 if (!err)
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600344 err = cadence_qspi_apb_write_execute(priv, op);
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530345 break;
346 default:
347 err = -1;
348 break;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100349 }
350
351 return err;
352}
353
Pratyush Yadav38b08522021-06-26 00:47:09 +0530354static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
355 const struct spi_mem_op *op)
356{
357 bool all_true, all_false;
358
359 all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
360 op->data.dtr;
361 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
362 !op->data.dtr;
363
364 /* Mixed DTR modes not supported. */
365 if (!(all_true || all_false))
366 return false;
367
368 if (all_true)
369 return spi_mem_dtr_supports_op(slave, op);
370 else
371 return spi_mem_default_supports_op(slave, op);
372}
373
Simon Glassd1998a92020-12-03 16:55:21 -0700374static int cadence_spi_of_to_plat(struct udevice *bus)
Stefan Roese10e8bf82014-11-07 12:37:49 +0100375{
Simon Glass0fd3d912020-12-22 19:30:28 -0700376 struct cadence_spi_plat *plat = dev_get_plat(bus);
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600377 struct cadence_spi_priv *priv = dev_get_priv(bus);
Simon Goldschmidt46b633d2019-05-09 22:11:56 +0200378 ofnode subnode;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100379
Ley Foon Tan6c353672018-05-07 17:42:55 +0800380 plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530381 plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
382 &plat->ahbsize);
Simon Goldschmidt46b633d2019-05-09 22:11:56 +0200383 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
384 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
385 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
386 plat->trigger_address = dev_read_u32_default(bus,
387 "cdns,trigger-address",
388 0);
Vignesh Raghavendraffab2122020-01-27 10:36:40 +0530389 /* Use DAC mode only when MMIO window is at least 8M wide */
390 if (plat->ahbsize >= SZ_8M)
Ashok Reddy Somaf7d4cab2022-08-24 05:38:47 -0600391 priv->use_dac_mode = true;
Stefan Roese10e8bf82014-11-07 12:37:49 +0100392
T Karthik Reddycf553bf2022-05-12 04:05:32 -0600393 plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
394
Stefan Roese10e8bf82014-11-07 12:37:49 +0100395 /* All other paramters are embedded in the child node */
Simon Goldschmidt46b633d2019-05-09 22:11:56 +0200396 subnode = dev_read_first_subnode(bus);
397 if (!ofnode_valid(subnode)) {
Stefan Roese10e8bf82014-11-07 12:37:49 +0100398 printf("Error: subnode with SPI flash config missing!\n");
399 return -ENODEV;
400 }
401
Chin Liang See040f4ba2015-10-17 08:32:14 -0500402 /* Use 500 KHz as a suitable default */
Simon Goldschmidt46b633d2019-05-09 22:11:56 +0200403 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
404 500000);
Chin Liang See040f4ba2015-10-17 08:32:14 -0500405
Stefan Roese10e8bf82014-11-07 12:37:49 +0100406 /* Read other parameters from DT */
Simon Goldschmidt46b633d2019-05-09 22:11:56 +0200407 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
408 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
409 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
410 200);
411 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
412 255);
413 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
414 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
Pratyush Yadavbd8c8dc2021-06-26 00:47:07 +0530415 /*
416 * Read delay should be an unsigned value but we use a signed integer
417 * so that negative values can indicate that the device tree did not
418 * specify any signed values and we need to perform the calibration
419 * sequence to find it out.
420 */
421 plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay",
422 -1);
Stefan Roese10e8bf82014-11-07 12:37:49 +0100423
424 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
425 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
426 plat->page_size);
427
428 return 0;
429}
430
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530431static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
432 .exec_op = cadence_spi_mem_exec_op,
Pratyush Yadav38b08522021-06-26 00:47:09 +0530433 .supports_op = cadence_spi_mem_supports_op,
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530434};
435
Stefan Roese10e8bf82014-11-07 12:37:49 +0100436static const struct dm_spi_ops cadence_spi_ops = {
Stefan Roese10e8bf82014-11-07 12:37:49 +0100437 .set_speed = cadence_spi_set_speed,
438 .set_mode = cadence_spi_set_mode,
Vignesh Raghavendrad6407722020-01-27 10:36:39 +0530439 .mem_ops = &cadence_spi_mem_ops,
Stefan Roese10e8bf82014-11-07 12:37:49 +0100440 /*
441 * cs_info is not needed, since we require all chip selects to be
442 * in the device tree explicitly
443 */
444};
445
446static const struct udevice_id cadence_spi_ids[] = {
Simon Goldschmidt2a3a9992018-11-02 11:54:51 +0100447 { .compatible = "cdns,qspi-nor" },
Vignesh Raghavendradaa94052019-12-05 15:46:07 +0530448 { .compatible = "ti,am654-ospi" },
Stefan Roese10e8bf82014-11-07 12:37:49 +0100449 { }
450};
451
452U_BOOT_DRIVER(cadence_spi) = {
453 .name = "cadence_spi",
454 .id = UCLASS_SPI,
455 .of_match = cadence_spi_ids,
456 .ops = &cadence_spi_ops,
Simon Glassd1998a92020-12-03 16:55:21 -0700457 .of_to_plat = cadence_spi_of_to_plat,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700458 .plat_auto = sizeof(struct cadence_spi_plat),
Simon Glass41575d82020-12-03 16:55:17 -0700459 .priv_auto = sizeof(struct cadence_spi_priv),
Stefan Roese10e8bf82014-11-07 12:37:49 +0100460 .probe = cadence_spi_probe,
Simon Goldschmidtac7e14a2019-03-01 20:12:35 +0100461 .remove = cadence_spi_remove,
462 .flags = DM_FLAG_OS_PREPARE,
Stefan Roese10e8bf82014-11-07 12:37:49 +0100463};