blob: b05ac0ade5b8ce86246af6b6a5a6c9f39d77a671 [file] [log] [blame]
Weijie Gaodd4fdc02020-11-12 16:35:52 +08001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8#ifndef __CONFIG_MT7620_H
9#define __CONFIG_MT7620_H
10
11#define CONFIG_SYS_HZ 1000
12#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
13
14#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
15
Weijie Gaodd4fdc02020-11-12 16:35:52 +080016#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
17
18#define CONFIG_SYS_SDRAM_BASE 0x80000000
Weijie Gaodd4fdc02020-11-12 16:35:52 +080019
20#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
21
22#define CONFIG_SYS_BOOTM_LEN 0x1000000
23
24#define CONFIG_SYS_MAXARGS 16
25#define CONFIG_SYS_CBSIZE 1024
26
27/* Serial common */
28#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
29
30/* SPL */
Weijie Gaodd4fdc02020-11-12 16:35:52 +080031
32#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
33#define CONFIG_SPL_BSS_START_ADDR 0x80010000
34#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
35#define CONFIG_SPL_MAX_SIZE 0x10000
36#define CONFIG_SPL_PAD_TO 0
37
38/* Dummy value */
39#define CONFIG_SYS_UBOOT_BASE 0
40
41#endif /* __CONFIG_MT7620_H */