blob: 073a179bafe7023f4a06aeb5f44ae20b05666cb0 [file] [log] [blame]
Wills Wang1d3d0f12016-03-16 16:59:52 +08001/*
2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Marek Vasut6b699742016-05-06 20:10:37 +02008#include <asm/errno.h>
Wills Wang1d3d0f12016-03-16 16:59:52 +08009#include <asm/io.h>
10#include <asm/addrspace.h>
11#include <asm/types.h>
12#include <mach/ath79.h>
13#include <mach/ar71xx_regs.h>
14
15void _machine_restart(void)
16{
17 void __iomem *base;
18 u32 reg = 0;
19
20 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
21 MAP_NOCACHE);
22 if (soc_is_ar71xx())
23 reg = AR71XX_RESET_REG_RESET_MODULE;
24 else if (soc_is_ar724x())
25 reg = AR724X_RESET_REG_RESET_MODULE;
26 else if (soc_is_ar913x())
27 reg = AR913X_RESET_REG_RESET_MODULE;
28 else if (soc_is_ar933x())
29 reg = AR933X_RESET_REG_RESET_MODULE;
30 else if (soc_is_ar934x())
31 reg = AR934X_RESET_REG_RESET_MODULE;
32 else if (soc_is_qca953x())
33 reg = QCA953X_RESET_REG_RESET_MODULE;
34 else if (soc_is_qca955x())
35 reg = QCA955X_RESET_REG_RESET_MODULE;
36 else if (soc_is_qca956x())
37 reg = QCA956X_RESET_REG_RESET_MODULE;
38 else
39 puts("Reset register not defined for this SOC\n");
40
41 if (reg)
42 setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
43
44 while (1)
45 /* NOP */;
46}
47
Wills Wang37523912016-05-30 22:54:50 +080048u32 ath79_get_bootstrap(void)
Wills Wang1d3d0f12016-03-16 16:59:52 +080049{
Marek Vasut43a092f2016-05-06 20:10:35 +020050 void __iomem *base;
Wills Wang1d3d0f12016-03-16 16:59:52 +080051 u32 reg = 0;
52
53 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
54 MAP_NOCACHE);
55 if (soc_is_ar933x())
56 reg = AR933X_RESET_REG_BOOTSTRAP;
57 else if (soc_is_ar934x())
58 reg = AR934X_RESET_REG_BOOTSTRAP;
59 else if (soc_is_qca953x())
60 reg = QCA953X_RESET_REG_BOOTSTRAP;
61 else if (soc_is_qca955x())
62 reg = QCA955X_RESET_REG_BOOTSTRAP;
63 else if (soc_is_qca956x())
64 reg = QCA956X_RESET_REG_BOOTSTRAP;
65 else
66 puts("Bootstrap register not defined for this SOC\n");
67
68 if (reg)
69 return readl(base + reg);
70
71 return 0;
72}
Marek Vasut6b699742016-05-06 20:10:37 +020073
Marek Vasut4771bbe2016-05-06 20:10:39 +020074static int eth_init_ar933x(void)
75{
76 void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
77 MAP_NOCACHE);
78 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
79 MAP_NOCACHE);
80 void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE,
81 MAP_NOCACHE);
82 const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
83 AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
Wills Wang42a3f3e2016-05-22 11:59:50 +080084 AR933X_RESET_ETH_SWITCH |
85 AR933X_RESET_ETH_SWITCH_ANALOG;
Marek Vasut4771bbe2016-05-06 20:10:39 +020086
87 /* Clear MDIO slave EN bit. */
88 clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
89 mdelay(10);
90
91 /* Get Atheros S26 PHY out of reset. */
Wills Wangca09e662016-05-30 22:54:54 +080092 clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
Marek Vasut4771bbe2016-05-06 20:10:39 +020093 0x1f, 0x10);
94 mdelay(10);
95
96 setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
97 mdelay(10);
98 clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
99 mdelay(10);
100
101 /* Configure AR93xx GMAC register. */
102 clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG,
103 AR933X_ETH_CFG_MII_GE0_MASTER |
104 AR933X_ETH_CFG_MII_GE0_SLAVE,
105 AR933X_ETH_CFG_MII_GE0_SLAVE);
106 return 0;
107}
108
109static int eth_init_ar934x(void)
110{
111 void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
112 MAP_NOCACHE);
113 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
114 MAP_NOCACHE);
115 void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE,
116 MAP_NOCACHE);
117 const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO |
118 AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO |
119 AR934X_RESET_ETH_SWITCH_ANALOG;
120 u32 reg;
121
122 reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP);
123 if (reg & AR934X_BOOTSTRAP_REF_CLK_40)
124 writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
125 else
126 writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
127 writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG);
128
129 setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
130 mdelay(1);
131 clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
132 mdelay(1);
133
134 /* Configure AR934x GMAC register. */
135 writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG);
136 return 0;
137}
138
Wills Wangcdeb68e2016-05-30 22:54:53 +0800139static int eth_init_qca953x(void)
140{
141 void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
142 MAP_NOCACHE);
143 const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
144 QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
145 QCA953X_RESET_ETH_SWITCH_ANALOG |
146 QCA953X_RESET_ETH_SWITCH;
147
148 setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
149 mdelay(1);
150 clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
151 mdelay(1);
152
153 return 0;
154}
155
Marek Vasut4771bbe2016-05-06 20:10:39 +0200156int ath79_eth_reset(void)
157{
158 /*
159 * Un-reset ethernet. DM still doesn't have any notion of reset
160 * framework, so we do it by hand here.
161 */
162 if (soc_is_ar933x())
163 return eth_init_ar933x();
164 if (soc_is_ar934x())
165 return eth_init_ar934x();
Wills Wangcdeb68e2016-05-30 22:54:53 +0800166 if (soc_is_qca953x())
167 return eth_init_qca953x();
Marek Vasut4771bbe2016-05-06 20:10:39 +0200168
169 return -EINVAL;
170}
171
Marek Vasut6b699742016-05-06 20:10:37 +0200172static int usb_reset_ar933x(void __iomem *reset_regs)
173{
174 /* Ungate the USB block */
175 setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
176 AR933X_RESET_USBSUS_OVERRIDE);
177 mdelay(1);
178 clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
179 AR933X_RESET_USB_HOST);
180 mdelay(1);
181 clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
182 AR933X_RESET_USB_PHY);
183 mdelay(1);
184
185 return 0;
186}
187
188static int usb_reset_ar934x(void __iomem *reset_regs)
189{
190 /* Ungate the USB block */
191 setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
192 AR934X_RESET_USBSUS_OVERRIDE);
193 mdelay(1);
194 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
195 AR934X_RESET_USB_PHY);
196 mdelay(1);
197 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
198 AR934X_RESET_USB_PHY_ANALOG);
199 mdelay(1);
200 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
201 AR934X_RESET_USB_HOST);
202 mdelay(1);
203
204 return 0;
205}
206
Wills Wangcdeb68e2016-05-30 22:54:53 +0800207static int usb_reset_qca953x(void __iomem *reset_regs)
208{
209 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
210 MAP_NOCACHE);
211
212 clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
213 0xf00, 0x200);
214 mdelay(10);
215
216 /* Ungate the USB block */
217 setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
218 QCA953X_RESET_USBSUS_OVERRIDE);
219 mdelay(1);
220 clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
221 QCA953X_RESET_USB_PHY);
222 mdelay(1);
223 clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
224 QCA953X_RESET_USB_PHY_ANALOG);
225 mdelay(1);
226 clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
227 QCA953X_RESET_USB_HOST);
228 mdelay(1);
229 clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
230 QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
231 mdelay(1);
232
233 return 0;
234}
235
Marek Vasut6b699742016-05-06 20:10:37 +0200236int ath79_usb_reset(void)
237{
238 void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
239 AR71XX_USB_CTRL_SIZE,
240 MAP_NOCACHE);
241 void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
242 AR71XX_RESET_SIZE,
243 MAP_NOCACHE);
244 /*
245 * Turn on the Buff and Desc swap bits.
246 * NOTE: This write into an undocumented register in mandatory to
247 * get the USB controller operational in BigEndian mode.
248 */
249 writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
250
251 if (soc_is_ar933x())
252 return usb_reset_ar933x(reset_regs);
253 if (soc_is_ar934x())
254 return usb_reset_ar934x(reset_regs);
Wills Wangcdeb68e2016-05-30 22:54:53 +0800255 if (soc_is_qca953x())
256 return usb_reset_qca953x(reset_regs);
Marek Vasut6b699742016-05-06 20:10:37 +0200257
258 return -EINVAL;
259}