| Chris Packham | 6cc8b5d | 2022-11-05 17:24:00 +1300 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Device Tree For RD-AC5X. |
| 4 | * |
| 5 | * Copyright (C) 2021 Marvell |
| 6 | * Copyright (C) 2022 Allied Telesis Labs |
| 7 | */ |
| 8 | /* |
| 9 | * Device Tree file for Marvell Alleycat 5X development board |
| 10 | * This board file supports the B configuration of the board |
| 11 | */ |
| 12 | |
| 13 | /dts-v1/; |
| 14 | |
| 15 | #include "ac5-98dx35xx.dtsi" |
| 16 | |
| 17 | / { |
| 18 | model = "Marvell RD-AC5X Board"; |
| 19 | compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5"; |
| 20 | |
| 21 | aliases { |
| 22 | serial0 = &uart0; |
| 23 | spiflash0 = &spiflash0; |
| 24 | gpio0 = &gpio0; |
| 25 | gpio1 = &gpio1; |
| 26 | ethernet0 = ð0; |
| 27 | ethernet1 = ð1; |
| 28 | spi0 = &spi0; |
| 29 | i2c0 = &i2c0; |
| 30 | i2c1 = &i2c1; |
| 31 | usb0 = &usb0; |
| 32 | usb1 = &usb1; |
| 33 | pinctrl0 = &pinctrl0; |
| 34 | sar-reg0 = "/config-space/sar-reg"; |
| 35 | }; |
| 36 | |
| 37 | usb1phy: usb-phy { |
| 38 | compatible = "usb-nop-xceiv"; |
| 39 | #phy-cells = <0>; |
| 40 | }; |
| 41 | |
| 42 | chosen { |
| 43 | stdout-path = "serial0:115200n8"; |
| 44 | }; |
| 45 | }; |
| 46 | |
| 47 | &uart0 { |
| 48 | status = "okay"; |
| 49 | }; |
| 50 | |
| 51 | &mdio { |
| 52 | phy0: ethernet-phy@0 { |
| 53 | reg = <0>; |
| 54 | }; |
| 55 | }; |
| 56 | |
| 57 | &i2c0 { |
| 58 | status = "okay"; |
| 59 | }; |
| 60 | |
| 61 | &i2c1 { |
| 62 | status = "okay"; |
| 63 | }; |
| 64 | |
| 65 | ð0 { |
| 66 | status = "okay"; |
| 67 | phy-handle = <&phy0>; |
| 68 | }; |
| 69 | |
| 70 | /* USB0 is a host USB */ |
| 71 | &usb0 { |
| 72 | status = "okay"; |
| 73 | }; |
| 74 | |
| 75 | /* USB1 is a peripheral USB */ |
| 76 | &usb1 { |
| 77 | status = "okay"; |
| 78 | phys = <&usb1phy>; |
| 79 | phy-names = "usb-phy"; |
| 80 | dr_mode = "peripheral"; |
| 81 | }; |
| 82 | |
| 83 | &spi0 { |
| 84 | status = "okay"; |
| 85 | |
| 86 | spiflash0: flash@0 { |
| 87 | compatible = "jedec,spi-nor"; |
| 88 | spi-max-frequency = <50000000>; |
| 89 | spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ |
| 90 | spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ |
| 91 | reg = <0>; |
| 92 | |
| 93 | #address-cells = <1>; |
| 94 | #size-cells = <1>; |
| 95 | }; |
| 96 | }; |
| 97 | |
| 98 | &pinctrl0 { |
| 99 | /* |
| 100 | * MPP Bus: MPP# mode# |
| 101 | * eMMC [0-11] 0x1 |
| 102 | * SPI[0] [12-17] 0x1 |
| 103 | * TSEN_INT [18] 0x1 |
| 104 | * DEV_INIT [19] 0x1 |
| 105 | * SPI[1] [20-23] 0x3 |
| 106 | * UART[1] [24-25] 0x3 |
| 107 | * I2C[0] [26-27] 0x1 |
| 108 | * XSMI[0] [28-29] 0x1 // SCH use SMI[0], reversed due to CPSS problem |
| 109 | * SMI[1] [30-31] 0x2 // SCH use XSMI[1], reversed due to CPSS problem |
| 110 | * UART[0] [32-33] 0x1 |
| 111 | * OOB_SMI [34-35] 0x1 |
| 112 | * PTP_CLK0_OUT [36] 0x1 |
| 113 | * PTP_PULSE_OUT [37] 0x1 |
| 114 | * RCVR_CLK_OUT [38] 0x1 |
| 115 | * GPIO(in/out) [39] 0x0 |
| 116 | * GPIO(in/out) [40] 0x0 |
| 117 | * PTP_REF_CLK [41] 0x1 |
| 118 | * PTP_CLK0 [42] 0x1 |
| 119 | * LED0_CLK [43] 0x1 |
| 120 | * LED0_STB [44] 0x1 |
| 121 | * LED0_DATA [45] 0x1 |
| 122 | */ |
| 123 | /* 0 1 2 3 4 5 6 7 8 9 */ |
| 124 | pin-func = < 1 1 1 1 1 1 1 1 1 1 |
| 125 | 1 1 1 1 1 1 1 1 1 1 |
| 126 | 3 3 3 3 3 3 1 1 1 1 |
| 127 | 2 2 1 1 1 1 1 1 1 0 |
| 128 | 0 1 1 1 1 1 >; |
| 129 | }; |