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Dave Liu7737d5c2006-11-03 12:11:15 -06001/*
Kumar Galaf8c42492010-09-30 09:14:40 -05002 * Copyright (C) 2005,2010 Freescale Semiconductor, Inc.
Dave Liu7737d5c2006-11-03 12:11:15 -06003 *
4 * Author: Shlomi Gridish
5 *
6 * Description: UCC GETH Driver -- PHY handling
Wolfgang Denkdd520bf2006-11-30 18:02:20 +01007 * Driver for UEC on QE
8 * Based on 8260_io/fcc_enet.c
Dave Liu7737d5c2006-11-03 12:11:15 -06009 *
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010010 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
Dave Liu7737d5c2006-11-03 12:11:15 -060012 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#include "common.h"
18#include "net.h"
19#include "malloc.h"
20#include "asm/errno.h"
21#include "asm/immap_qe.h"
22#include "asm/io.h"
23#include "qe.h"
24#include "uccf.h"
25#include "uec.h"
26#include "uec_phy.h"
27#include "miiphy.h"
28
Dave Liu7737d5c2006-11-03 12:11:15 -060029#define ugphy_printk(format, arg...) \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010030 printf(format "\n", ## arg)
Dave Liu7737d5c2006-11-03 12:11:15 -060031
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010032#define ugphy_dbg(format, arg...) \
33 ugphy_printk(format , ## arg)
34#define ugphy_err(format, arg...) \
35 ugphy_printk(format , ## arg)
36#define ugphy_info(format, arg...) \
37 ugphy_printk(format , ## arg)
38#define ugphy_warn(format, arg...) \
39 ugphy_printk(format , ## arg)
Dave Liu7737d5c2006-11-03 12:11:15 -060040
41#ifdef UEC_VERBOSE_DEBUG
42#define ugphy_vdbg ugphy_dbg
43#else
44#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
45#endif /* UEC_VERBOSE_DEBUG */
46
Richard Retanubunedf3fe72008-10-23 09:08:18 -040047/*--------------------------------------------------------------------+
48 * Fixed PHY (PHY-less) support for Ethernet Ports.
49 *
Stefan Roesea47a12b2010-04-15 16:07:28 +020050 * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
Richard Retanubunedf3fe72008-10-23 09:08:18 -040051 *--------------------------------------------------------------------*/
52
53/*
Richard Retanubun1443cd72009-07-01 14:04:05 -040054 * Some boards do not have a PHY for each ethernet port. These ports are known
55 * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
56 * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
57 * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
58 * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
59 * speed and duplex should be for the port.
Richard Retanubunedf3fe72008-10-23 09:08:18 -040060 *
Richard Retanubun1443cd72009-07-01 14:04:05 -040061 * Example board header configuration file:
Richard Retanubunedf3fe72008-10-23 09:08:18 -040062 * #define CONFIG_FIXED_PHY 0xFFFFFFFF
Richard Retanubun1443cd72009-07-01 14:04:05 -040063 * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
Richard Retanubunedf3fe72008-10-23 09:08:18 -040064 *
Richard Retanubun1443cd72009-07-01 14:04:05 -040065 * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
66 * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
67 * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
68 * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
Richard Retanubunedf3fe72008-10-23 09:08:18 -040069 *
Richard Retanubun1443cd72009-07-01 14:04:05 -040070 * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
71 * {name, speed, duplex},
Richard Retanubunedf3fe72008-10-23 09:08:18 -040072 *
73 * #define CONFIG_SYS_FIXED_PHY_PORTS \
Kim Phillips78b7a8e2010-07-26 18:34:57 -050074 * CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
75 * CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
Richard Retanubunedf3fe72008-10-23 09:08:18 -040076 */
77
78#ifndef CONFIG_FIXED_PHY
79#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
80#endif
81
82#ifndef CONFIG_SYS_FIXED_PHY_PORTS
83#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
84#endif
85
86struct fixed_phy_port {
Richard Retanubun1443cd72009-07-01 14:04:05 -040087 char name[NAMESIZE]; /* ethernet port name */
Richard Retanubunedf3fe72008-10-23 09:08:18 -040088 unsigned int speed; /* specified speed 10,100 or 1000 */
89 unsigned int duplex; /* specified duplex FULL or HALF */
90};
91
92static const struct fixed_phy_port fixed_phy_port[] = {
93 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
94};
95
Richard Retanubun23c34af2009-06-17 16:00:41 -040096/*--------------------------------------------------------------------+
97 * BitBang MII support for ethernet ports
98 *
99 * Based from MPC8560ADS implementation
100 *--------------------------------------------------------------------*/
101/*
102 * Example board header file to define bitbang ethernet ports:
103 *
104 * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500105 * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
Richard Retanubun23c34af2009-06-17 16:00:41 -0400106*/
107#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
108#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
109#endif
110
111#if defined(CONFIG_BITBANGMII)
112static const char *bitbang_phy_port[] = {
113 CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
114};
115#endif /* CONFIG_BITBANGMII */
116
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100117static void config_genmii_advert (struct uec_mii_info *mii_info);
118static void genmii_setup_forced (struct uec_mii_info *mii_info);
119static void genmii_restart_aneg (struct uec_mii_info *mii_info);
120static int gbit_config_aneg (struct uec_mii_info *mii_info);
121static int genmii_config_aneg (struct uec_mii_info *mii_info);
122static int genmii_update_link (struct uec_mii_info *mii_info);
123static int genmii_read_status (struct uec_mii_info *mii_info);
124u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
125void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
Dave Liu7737d5c2006-11-03 12:11:15 -0600126
127/* Write value to the PHY for this device to the register at regnum, */
128/* waiting until the write is done before it returns. All PHY */
129/* configuration has to be done through the TSEC1 MIIM regs */
Andy Flemingda9d4612007-08-14 00:14:25 -0500130void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
Dave Liu7737d5c2006-11-03 12:11:15 -0600131{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100132 uec_private_t *ugeth = (uec_private_t *) dev->priv;
Andy Flemingda9d4612007-08-14 00:14:25 -0500133 uec_mii_t *ug_regs;
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100134 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
135 u32 tmp_reg;
Dave Liu7737d5c2006-11-03 12:11:15 -0600136
Richard Retanubun23c34af2009-06-17 16:00:41 -0400137
138#if defined(CONFIG_BITBANGMII)
139 u32 i = 0;
140
141 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
142 if (strncmp(dev->name, bitbang_phy_port[i],
143 sizeof(dev->name)) == 0) {
144 (void)bb_miiphy_write(NULL, mii_id, regnum, value);
145 return;
146 }
147 }
148#endif /* CONFIG_BITBANGMII */
149
Andy Flemingda9d4612007-08-14 00:14:25 -0500150 ug_regs = ugeth->uec_mii_regs;
Dave Liu7737d5c2006-11-03 12:11:15 -0600151
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100152 /* Stop the MII management read cycle */
153 out_be32 (&ug_regs->miimcom, 0);
154 /* Setting up the MII Mangement Address Register */
155 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
156 out_be32 (&ug_regs->miimadd, tmp_reg);
Dave Liu7737d5c2006-11-03 12:11:15 -0600157
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100158 /* Setting up the MII Mangement Control Register with the value */
159 out_be32 (&ug_regs->miimcon, (u32) value);
Kim Phillipsee62ed32008-01-15 14:11:00 -0600160 sync();
Dave Liu7737d5c2006-11-03 12:11:15 -0600161
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100162 /* Wait till MII management write is complete */
163 while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
Dave Liu7737d5c2006-11-03 12:11:15 -0600164}
165
166/* Reads from register regnum in the PHY for device dev, */
167/* returning the value. Clears miimcom first. All PHY */
168/* configuration has to be done through the TSEC1 MIIM regs */
Andy Flemingda9d4612007-08-14 00:14:25 -0500169int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
Dave Liu7737d5c2006-11-03 12:11:15 -0600170{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100171 uec_private_t *ugeth = (uec_private_t *) dev->priv;
Andy Flemingda9d4612007-08-14 00:14:25 -0500172 uec_mii_t *ug_regs;
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100173 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
174 u32 tmp_reg;
175 u16 value;
Dave Liu7737d5c2006-11-03 12:11:15 -0600176
Richard Retanubun23c34af2009-06-17 16:00:41 -0400177
178#if defined(CONFIG_BITBANGMII)
179 u32 i = 0;
180
181 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
182 if (strncmp(dev->name, bitbang_phy_port[i],
183 sizeof(dev->name)) == 0) {
184 (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
185 return (value);
186 }
187 }
188#endif /* CONFIG_BITBANGMII */
189
Andy Flemingda9d4612007-08-14 00:14:25 -0500190 ug_regs = ugeth->uec_mii_regs;
Dave Liu7737d5c2006-11-03 12:11:15 -0600191
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100192 /* Setting up the MII Mangement Address Register */
193 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
194 out_be32 (&ug_regs->miimadd, tmp_reg);
Dave Liu7737d5c2006-11-03 12:11:15 -0600195
Kim Phillipsee62ed32008-01-15 14:11:00 -0600196 /* clear MII management command cycle */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100197 out_be32 (&ug_regs->miimcom, 0);
Kim Phillipsee62ed32008-01-15 14:11:00 -0600198 sync();
199
200 /* Perform an MII management read cycle */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100201 out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
Dave Liu7737d5c2006-11-03 12:11:15 -0600202
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100203 /* Wait till MII management write is complete */
204 while ((in_be32 (&ug_regs->miimind)) &
205 (MIIMIND_NOT_VALID | MIIMIND_BUSY));
Dave Liu7737d5c2006-11-03 12:11:15 -0600206
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100207 /* Read MII management status */
208 value = (u16) in_be32 (&ug_regs->miimstat);
209 if (value == 0xffff)
Joakim Tjernlund84a30472008-01-16 09:40:41 +0100210 ugphy_vdbg
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100211 ("read wrong value : mii_id %d,mii_reg %d, base %08x",
212 mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
Dave Liu7737d5c2006-11-03 12:11:15 -0600213
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100214 return (value);
Dave Liu7737d5c2006-11-03 12:11:15 -0600215}
216
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100217void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600218{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100219 if (mii_info->phyinfo->ack_interrupt)
220 mii_info->phyinfo->ack_interrupt (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600221}
222
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100223void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
224 u32 interrupts)
Dave Liu7737d5c2006-11-03 12:11:15 -0600225{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100226 mii_info->interrupts = interrupts;
227 if (mii_info->phyinfo->config_intr)
228 mii_info->phyinfo->config_intr (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600229}
230
231/* Writes MII_ADVERTISE with the appropriate values, after
232 * sanitizing advertise to make sure only supported features
233 * are advertised
234 */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100235static void config_genmii_advert (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600236{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100237 u32 advertise;
238 u16 adv;
Dave Liu7737d5c2006-11-03 12:11:15 -0600239
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100240 /* Only allow advertising what this PHY supports */
241 mii_info->advertising &= mii_info->phyinfo->features;
242 advertise = mii_info->advertising;
Dave Liu7737d5c2006-11-03 12:11:15 -0600243
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100244 /* Setup standard advertisement */
245 adv = phy_read (mii_info, PHY_ANAR);
246 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
247 if (advertise & ADVERTISED_10baseT_Half)
248 adv |= ADVERTISE_10HALF;
249 if (advertise & ADVERTISED_10baseT_Full)
250 adv |= ADVERTISE_10FULL;
251 if (advertise & ADVERTISED_100baseT_Half)
252 adv |= ADVERTISE_100HALF;
253 if (advertise & ADVERTISED_100baseT_Full)
254 adv |= ADVERTISE_100FULL;
255 phy_write (mii_info, PHY_ANAR, adv);
Dave Liu7737d5c2006-11-03 12:11:15 -0600256}
257
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100258static void genmii_setup_forced (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600259{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100260 u16 ctrl;
261 u32 features = mii_info->phyinfo->features;
Dave Liu7737d5c2006-11-03 12:11:15 -0600262
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100263 ctrl = phy_read (mii_info, PHY_BMCR);
Dave Liu7737d5c2006-11-03 12:11:15 -0600264
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100265 ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
266 PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
267 ctrl |= PHY_BMCR_RESET;
Dave Liu7737d5c2006-11-03 12:11:15 -0600268
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100269 switch (mii_info->speed) {
270 case SPEED_1000:
271 if (features & (SUPPORTED_1000baseT_Half
272 | SUPPORTED_1000baseT_Full)) {
273 ctrl |= PHY_BMCR_1000_MBPS;
274 break;
275 }
276 mii_info->speed = SPEED_100;
277 case SPEED_100:
278 if (features & (SUPPORTED_100baseT_Half
279 | SUPPORTED_100baseT_Full)) {
280 ctrl |= PHY_BMCR_100_MBPS;
281 break;
282 }
283 mii_info->speed = SPEED_10;
284 case SPEED_10:
285 if (features & (SUPPORTED_10baseT_Half
286 | SUPPORTED_10baseT_Full))
287 break;
288 default: /* Unsupported speed! */
289 ugphy_err ("%s: Bad speed!", mii_info->dev->name);
290 break;
291 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600292
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100293 phy_write (mii_info, PHY_BMCR, ctrl);
Dave Liu7737d5c2006-11-03 12:11:15 -0600294}
295
296/* Enable and Restart Autonegotiation */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100297static void genmii_restart_aneg (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600298{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100299 u16 ctl;
Dave Liu7737d5c2006-11-03 12:11:15 -0600300
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100301 ctl = phy_read (mii_info, PHY_BMCR);
302 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
303 phy_write (mii_info, PHY_BMCR, ctl);
Dave Liu7737d5c2006-11-03 12:11:15 -0600304}
305
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100306static int gbit_config_aneg (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600307{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100308 u16 adv;
309 u32 advertise;
Dave Liu7737d5c2006-11-03 12:11:15 -0600310
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100311 if (mii_info->autoneg) {
312 /* Configure the ADVERTISE register */
313 config_genmii_advert (mii_info);
314 advertise = mii_info->advertising;
Dave Liu7737d5c2006-11-03 12:11:15 -0600315
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100316 adv = phy_read (mii_info, MII_1000BASETCONTROL);
317 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
318 MII_1000BASETCONTROL_HALFDUPLEXCAP);
319 if (advertise & SUPPORTED_1000baseT_Half)
320 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
321 if (advertise & SUPPORTED_1000baseT_Full)
322 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
323 phy_write (mii_info, MII_1000BASETCONTROL, adv);
Dave Liu7737d5c2006-11-03 12:11:15 -0600324
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100325 /* Start/Restart aneg */
326 genmii_restart_aneg (mii_info);
327 } else
328 genmii_setup_forced (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600329
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100330 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600331}
332
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100333static int marvell_config_aneg (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600334{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100335 /* The Marvell PHY has an errata which requires
336 * that certain registers get written in order
337 * to restart autonegotiation */
338 phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
Dave Liu7737d5c2006-11-03 12:11:15 -0600339
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100340 phy_write (mii_info, 0x1d, 0x1f);
341 phy_write (mii_info, 0x1e, 0x200c);
342 phy_write (mii_info, 0x1d, 0x5);
343 phy_write (mii_info, 0x1e, 0);
344 phy_write (mii_info, 0x1e, 0x100);
Dave Liu7737d5c2006-11-03 12:11:15 -0600345
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100346 gbit_config_aneg (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600347
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100348 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600349}
350
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100351static int genmii_config_aneg (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600352{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100353 if (mii_info->autoneg) {
Joakim Tjernlundf29c1812010-08-10 16:36:49 +0200354 /* Speed up the common case, if link is already up, speed and
355 duplex match, skip auto neg as it already matches */
356 if (!genmii_read_status(mii_info) && mii_info->link)
357 if (mii_info->duplex == DUPLEX_FULL &&
358 mii_info->speed == SPEED_100)
359 if (mii_info->advertising &
360 ADVERTISED_100baseT_Full)
361 return 0;
362
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100363 config_genmii_advert (mii_info);
364 genmii_restart_aneg (mii_info);
365 } else
366 genmii_setup_forced (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600367
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100368 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600369}
370
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100371static int genmii_update_link (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600372{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100373 u16 status;
Dave Liu7737d5c2006-11-03 12:11:15 -0600374
Kim Phillipsee62ed32008-01-15 14:11:00 -0600375 /* Status is read once to clear old link state */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100376 phy_read (mii_info, PHY_BMSR);
Dave Liu7737d5c2006-11-03 12:11:15 -0600377
Kim Phillipsee62ed32008-01-15 14:11:00 -0600378 /*
379 * Wait if the link is up, and autonegotiation is in progress
380 * (ie - we're capable and it's not done)
381 */
382 status = phy_read(mii_info, PHY_BMSR);
383 if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE)
384 && !(status & PHY_BMSR_AUTN_COMP)) {
385 int i = 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600386
Kim Phillipsee62ed32008-01-15 14:11:00 -0600387 while (!(status & PHY_BMSR_AUTN_COMP)) {
388 /*
389 * Timeout reached ?
390 */
391 if (i > UGETH_AN_TIMEOUT) {
392 mii_info->link = 0;
393 return 0;
394 }
395
Kim Phillipsf30b61542008-02-27 16:08:22 -0600396 i++;
Kim Phillipsee62ed32008-01-15 14:11:00 -0600397 udelay(1000); /* 1 ms */
398 status = phy_read(mii_info, PHY_BMSR);
399 }
400 mii_info->link = 1;
Kim Phillipsee62ed32008-01-15 14:11:00 -0600401 } else {
402 if (status & PHY_BMSR_LS)
403 mii_info->link = 1;
404 else
405 mii_info->link = 0;
406 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600407
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100408 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600409}
410
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100411static int genmii_read_status (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600412{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100413 u16 status;
414 int err;
Dave Liu7737d5c2006-11-03 12:11:15 -0600415
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100416 /* Update the link, but return if there
417 * was an error */
418 err = genmii_update_link (mii_info);
419 if (err)
420 return err;
Dave Liu7737d5c2006-11-03 12:11:15 -0600421
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100422 if (mii_info->autoneg) {
Anton Vorontsov91cdaa32008-03-24 20:46:24 +0300423 status = phy_read(mii_info, MII_1000BASETSTATUS);
Dave Liu7737d5c2006-11-03 12:11:15 -0600424
Anton Vorontsov91cdaa32008-03-24 20:46:24 +0300425 if (status & (LPA_1000FULL | LPA_1000HALF)) {
426 mii_info->speed = SPEED_1000;
427 if (status & LPA_1000FULL)
428 mii_info->duplex = DUPLEX_FULL;
429 else
430 mii_info->duplex = DUPLEX_HALF;
431 } else {
432 status = phy_read(mii_info, PHY_ANLPAR);
433
434 if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
435 mii_info->duplex = DUPLEX_FULL;
436 else
437 mii_info->duplex = DUPLEX_HALF;
438 if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
439 mii_info->speed = SPEED_100;
440 else
441 mii_info->speed = SPEED_10;
442 }
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100443 mii_info->pause = 0;
444 }
445 /* On non-aneg, we assume what we put in BMCR is the speed,
446 * though magic-aneg shouldn't prevent this case from occurring
447 */
Dave Liu7737d5c2006-11-03 12:11:15 -0600448
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100449 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600450}
451
Anton Vorontsov300615d2008-03-24 20:46:34 +0300452static int bcm_init(struct uec_mii_info *mii_info)
453{
454 struct eth_device *edev = mii_info->dev;
455 uec_private_t *uec = edev->priv;
456
457 gbit_config_aneg(mii_info);
458
Heiko Schocher582c55a2010-01-20 09:04:28 +0100459 if ((uec->uec_info->enet_interface_type == RGMII_RXID) &&
460 (uec->uec_info->speed == 1000)) {
Anton Vorontsov300615d2008-03-24 20:46:34 +0300461 u16 val;
462 int cnt = 50;
463
464 /* Wait for aneg to complete. */
465 do
466 val = phy_read(mii_info, PHY_BMSR);
467 while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
468
469 /* Set RDX clk delay. */
470 phy_write(mii_info, 0x18, 0x7 | (7 << 12));
471
472 val = phy_read(mii_info, 0x18);
473 /* Set RDX-RXC skew. */
474 val |= (1 << 8);
475 val |= (7 | (7 << 12));
476 /* Write bits 14:0. */
477 val |= (1 << 15);
478 phy_write(mii_info, 0x18, val);
479 }
480
481 return 0;
482}
483
Haiying Wang41410ee2008-09-24 11:42:12 -0500484static int marvell_init(struct uec_mii_info *mii_info)
485{
486 struct eth_device *edev = mii_info->dev;
487 uec_private_t *uec = edev->priv;
Kumar Galaf8c42492010-09-30 09:14:40 -0500488 enum fsl_phy_enet_if iface = uec->uec_info->enet_interface_type;
Heiko Schocher582c55a2010-01-20 09:04:28 +0100489 int speed = uec->uec_info->speed;
Haiying Wang41410ee2008-09-24 11:42:12 -0500490
Heiko Schocher582c55a2010-01-20 09:04:28 +0100491 if ((speed == 1000) &&
492 (iface == RGMII_ID ||
493 iface == RGMII_RXID ||
494 iface == RGMII_TXID)) {
Haiying Wang41410ee2008-09-24 11:42:12 -0500495 int temp;
496
497 temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR);
Heiko Schocher582c55a2010-01-20 09:04:28 +0100498 if (iface == RGMII_ID) {
Anton Vorontsov6185f802009-09-16 23:21:53 +0400499 temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
Heiko Schocher582c55a2010-01-20 09:04:28 +0100500 } else if (iface == RGMII_RXID) {
Anton Vorontsov6185f802009-09-16 23:21:53 +0400501 temp &= ~MII_M1111_TX_DELAY;
502 temp |= MII_M1111_RX_DELAY;
Heiko Schocher582c55a2010-01-20 09:04:28 +0100503 } else if (iface == RGMII_TXID) {
Anton Vorontsov6185f802009-09-16 23:21:53 +0400504 temp &= ~MII_M1111_RX_DELAY;
505 temp |= MII_M1111_TX_DELAY;
506 }
Haiying Wang41410ee2008-09-24 11:42:12 -0500507 phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
508
509 temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR);
510 temp &= ~MII_M1111_HWCFG_MODE_MASK;
511 temp |= MII_M1111_HWCFG_MODE_RGMII;
512 phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
513
514 phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
515 }
516
517 return 0;
518}
519
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100520static int marvell_read_status (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600521{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100522 u16 status;
523 int err;
Dave Liu7737d5c2006-11-03 12:11:15 -0600524
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100525 /* Update the link, but return if there
526 * was an error */
527 err = genmii_update_link (mii_info);
528 if (err)
529 return err;
Dave Liu7737d5c2006-11-03 12:11:15 -0600530
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100531 /* If the link is up, read the speed and duplex */
532 /* If we aren't autonegotiating, assume speeds
533 * are as set */
534 if (mii_info->autoneg && mii_info->link) {
535 int speed;
Dave Liu7737d5c2006-11-03 12:11:15 -0600536
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100537 status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
Dave Liu7737d5c2006-11-03 12:11:15 -0600538
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100539 /* Get the duplexity */
540 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
541 mii_info->duplex = DUPLEX_FULL;
542 else
543 mii_info->duplex = DUPLEX_HALF;
Dave Liu7737d5c2006-11-03 12:11:15 -0600544
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100545 /* Get the speed */
546 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
547 switch (speed) {
548 case MII_M1011_PHY_SPEC_STATUS_1000:
549 mii_info->speed = SPEED_1000;
550 break;
551 case MII_M1011_PHY_SPEC_STATUS_100:
552 mii_info->speed = SPEED_100;
553 break;
554 default:
555 mii_info->speed = SPEED_10;
556 break;
557 }
558 mii_info->pause = 0;
559 }
560
561 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600562}
563
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100564static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600565{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100566 /* Clear the interrupts by reading the reg */
567 phy_read (mii_info, MII_M1011_IEVENT);
Dave Liu7737d5c2006-11-03 12:11:15 -0600568
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100569 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600570}
571
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100572static int marvell_config_intr (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600573{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100574 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
575 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
576 else
577 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
Dave Liu7737d5c2006-11-03 12:11:15 -0600578
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100579 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600580}
581
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100582static int dm9161_init (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600583{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100584 /* Reset the PHY */
585 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
586 PHY_BMCR_RESET);
587 /* PHY and MAC connect */
588 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
589 ~PHY_BMCR_ISO);
Kim Phillipsee62ed32008-01-15 14:11:00 -0600590
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100591 phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
Kim Phillipsee62ed32008-01-15 14:11:00 -0600592
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100593 config_genmii_advert (mii_info);
594 /* Start/restart aneg */
595 genmii_config_aneg (mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600596
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100597 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600598}
599
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100600static int dm9161_config_aneg (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600601{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100602 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600603}
604
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100605static int dm9161_read_status (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600606{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100607 u16 status;
608 int err;
Dave Liu7737d5c2006-11-03 12:11:15 -0600609
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100610 /* Update the link, but return if there was an error */
611 err = genmii_update_link (mii_info);
612 if (err)
613 return err;
614 /* If the link is up, read the speed and duplex
615 If we aren't autonegotiating assume speeds are as set */
616 if (mii_info->autoneg && mii_info->link) {
617 status = phy_read (mii_info, MII_DM9161_SCSR);
618 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
619 mii_info->speed = SPEED_100;
620 else
621 mii_info->speed = SPEED_10;
Dave Liu7737d5c2006-11-03 12:11:15 -0600622
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100623 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
624 mii_info->duplex = DUPLEX_FULL;
625 else
626 mii_info->duplex = DUPLEX_HALF;
627 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600628
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100629 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600630}
631
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100632static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600633{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100634 /* Clear the interrupt by reading the reg */
635 phy_read (mii_info, MII_DM9161_INTR);
Dave Liu7737d5c2006-11-03 12:11:15 -0600636
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100637 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600638}
639
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100640static int dm9161_config_intr (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600641{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100642 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
643 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
644 else
645 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
Dave Liu7737d5c2006-11-03 12:11:15 -0600646
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100647 return 0;
Dave Liu7737d5c2006-11-03 12:11:15 -0600648}
649
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100650static void dm9161_close (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600651{
652}
653
Richard Retanubunedf3fe72008-10-23 09:08:18 -0400654static int fixed_phy_aneg (struct uec_mii_info *mii_info)
655{
656 mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
657 return 0;
658}
659
660static int fixed_phy_read_status (struct uec_mii_info *mii_info)
661{
662 int i = 0;
663
664 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
Richard Retanubun1443cd72009-07-01 14:04:05 -0400665 if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
666 strlen(mii_info->dev->name)) == 0) {
Richard Retanubunedf3fe72008-10-23 09:08:18 -0400667 mii_info->speed = fixed_phy_port[i].speed;
668 mii_info->duplex = fixed_phy_port[i].duplex;
669 mii_info->link = 1; /* Link is always UP */
670 mii_info->pause = 0;
671 break;
672 }
673 }
674 return 0;
675}
676
Heiko Schocher8b69b562008-11-20 09:57:14 +0100677static int smsc_config_aneg (struct uec_mii_info *mii_info)
678{
679 return 0;
680}
681
682static int smsc_read_status (struct uec_mii_info *mii_info)
683{
684 u16 status;
685 int err;
686
687 /* Update the link, but return if there
688 * was an error */
689 err = genmii_update_link (mii_info);
690 if (err)
691 return err;
692
693 /* If the link is up, read the speed and duplex */
694 /* If we aren't autonegotiating, assume speeds
695 * are as set */
696 if (mii_info->autoneg && mii_info->link) {
697 int val;
698
699 status = phy_read (mii_info, 0x1f);
700 val = (status & 0x1c) >> 2;
701
702 switch (val) {
703 case 1:
704 mii_info->duplex = DUPLEX_HALF;
705 mii_info->speed = SPEED_10;
706 break;
707 case 5:
708 mii_info->duplex = DUPLEX_FULL;
709 mii_info->speed = SPEED_10;
710 break;
711 case 2:
712 mii_info->duplex = DUPLEX_HALF;
713 mii_info->speed = SPEED_100;
714 break;
715 case 6:
716 mii_info->duplex = DUPLEX_FULL;
717 mii_info->speed = SPEED_100;
718 break;
719 }
720 mii_info->pause = 0;
721 }
722
723 return 0;
724}
725
Dave Liu7737d5c2006-11-03 12:11:15 -0600726static struct phy_info phy_info_dm9161 = {
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100727 .phy_id = 0x0181b880,
728 .phy_id_mask = 0x0ffffff0,
729 .name = "Davicom DM9161E",
730 .init = dm9161_init,
731 .config_aneg = dm9161_config_aneg,
732 .read_status = dm9161_read_status,
733 .close = dm9161_close,
Dave Liu7737d5c2006-11-03 12:11:15 -0600734};
735
736static struct phy_info phy_info_dm9161a = {
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100737 .phy_id = 0x0181b8a0,
738 .phy_id_mask = 0x0ffffff0,
739 .name = "Davicom DM9161A",
740 .features = MII_BASIC_FEATURES,
741 .init = dm9161_init,
742 .config_aneg = dm9161_config_aneg,
743 .read_status = dm9161_read_status,
744 .ack_interrupt = dm9161_ack_interrupt,
745 .config_intr = dm9161_config_intr,
746 .close = dm9161_close,
Dave Liu7737d5c2006-11-03 12:11:15 -0600747};
748
749static struct phy_info phy_info_marvell = {
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100750 .phy_id = 0x01410c00,
751 .phy_id_mask = 0xffffff00,
752 .name = "Marvell 88E11x1",
753 .features = MII_GBIT_FEATURES,
Haiying Wang41410ee2008-09-24 11:42:12 -0500754 .init = &marvell_init,
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100755 .config_aneg = &marvell_config_aneg,
756 .read_status = &marvell_read_status,
757 .ack_interrupt = &marvell_ack_interrupt,
758 .config_intr = &marvell_config_intr,
Dave Liu7737d5c2006-11-03 12:11:15 -0600759};
760
Anton Vorontsov300615d2008-03-24 20:46:34 +0300761static struct phy_info phy_info_bcm5481 = {
762 .phy_id = 0x0143bca0,
763 .phy_id_mask = 0xffffff0,
764 .name = "Broadcom 5481",
765 .features = MII_GBIT_FEATURES,
766 .read_status = genmii_read_status,
767 .init = bcm_init,
768};
769
Richard Retanubunedf3fe72008-10-23 09:08:18 -0400770static struct phy_info phy_info_fixedphy = {
771 .phy_id = CONFIG_FIXED_PHY,
772 .phy_id_mask = CONFIG_FIXED_PHY,
773 .name = "Fixed PHY",
774 .config_aneg = fixed_phy_aneg,
775 .read_status = fixed_phy_read_status,
776};
777
Heiko Schocher8b69b562008-11-20 09:57:14 +0100778static struct phy_info phy_info_smsclan8700 = {
779 .phy_id = 0x0007c0c0,
780 .phy_id_mask = 0xfffffff0,
781 .name = "SMSC LAN8700",
782 .features = MII_BASIC_FEATURES,
783 .config_aneg = smsc_config_aneg,
784 .read_status = smsc_read_status,
785};
786
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100787static struct phy_info phy_info_genmii = {
788 .phy_id = 0x00000000,
789 .phy_id_mask = 0x00000000,
790 .name = "Generic MII",
791 .features = MII_BASIC_FEATURES,
792 .config_aneg = genmii_config_aneg,
793 .read_status = genmii_read_status,
Dave Liu7737d5c2006-11-03 12:11:15 -0600794};
795
796static struct phy_info *phy_info[] = {
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100797 &phy_info_dm9161,
798 &phy_info_dm9161a,
799 &phy_info_marvell,
Anton Vorontsov300615d2008-03-24 20:46:34 +0300800 &phy_info_bcm5481,
Heiko Schocher8b69b562008-11-20 09:57:14 +0100801 &phy_info_smsclan8700,
Richard Retanubunedf3fe72008-10-23 09:08:18 -0400802 &phy_info_fixedphy,
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100803 &phy_info_genmii,
804 NULL
Dave Liu7737d5c2006-11-03 12:11:15 -0600805};
806
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100807u16 phy_read (struct uec_mii_info *mii_info, u16 regnum)
Dave Liu7737d5c2006-11-03 12:11:15 -0600808{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100809 return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
Dave Liu7737d5c2006-11-03 12:11:15 -0600810}
811
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100812void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
Dave Liu7737d5c2006-11-03 12:11:15 -0600813{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100814 mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
Dave Liu7737d5c2006-11-03 12:11:15 -0600815}
816
817/* Use the PHY ID registers to determine what type of PHY is attached
818 * to device dev. return a struct phy_info structure describing that PHY
819 */
Andy Flemingda9d4612007-08-14 00:14:25 -0500820struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
Dave Liu7737d5c2006-11-03 12:11:15 -0600821{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100822 u16 phy_reg;
823 u32 phy_ID;
824 int i;
825 struct phy_info *theInfo = NULL;
Dave Liu7737d5c2006-11-03 12:11:15 -0600826
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100827 /* Grab the bits from PHYIR1, and put them in the upper half */
828 phy_reg = phy_read (mii_info, PHY_PHYIDR1);
829 phy_ID = (phy_reg & 0xffff) << 16;
Dave Liu7737d5c2006-11-03 12:11:15 -0600830
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100831 /* Grab the bits from PHYIR2, and put them in the lower half */
832 phy_reg = phy_read (mii_info, PHY_PHYIDR2);
833 phy_ID |= (phy_reg & 0xffff);
Dave Liu7737d5c2006-11-03 12:11:15 -0600834
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100835 /* loop through all the known PHY types, and find one that */
836 /* matches the ID we read from the PHY. */
837 for (i = 0; phy_info[i]; i++)
838 if (phy_info[i]->phy_id ==
839 (phy_ID & phy_info[i]->phy_id_mask)) {
840 theInfo = phy_info[i];
841 break;
842 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600843
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100844 /* This shouldn't happen, as we have generic PHY support */
845 if (theInfo == NULL) {
846 ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
847 return NULL;
848 } else {
849 ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
850 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600851
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100852 return theInfo;
Dave Liu7737d5c2006-11-03 12:11:15 -0600853}
854
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100855void marvell_phy_interface_mode (struct eth_device *dev,
Kumar Galaf8c42492010-09-30 09:14:40 -0500856 enum fsl_phy_enet_if type,
Heiko Schocher582c55a2010-01-20 09:04:28 +0100857 int speed
858 )
Dave Liu7737d5c2006-11-03 12:11:15 -0600859{
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100860 uec_private_t *uec = (uec_private_t *) dev->priv;
861 struct uec_mii_info *mii_info;
Kim Phillipsf655ade2008-02-27 15:06:39 -0600862 u16 status;
Dave Liu7737d5c2006-11-03 12:11:15 -0600863
864 if (!uec->mii_info) {
Kim Phillipsf30b61542008-02-27 16:08:22 -0600865 printf ("%s: the PHY not initialized\n", __FUNCTION__);
Dave Liu7737d5c2006-11-03 12:11:15 -0600866 return;
867 }
868 mii_info = uec->mii_info;
869
Heiko Schocher582c55a2010-01-20 09:04:28 +0100870 if (type == RGMII) {
871 if (speed == 100) {
872 phy_write (mii_info, 0x00, 0x9140);
873 phy_write (mii_info, 0x1d, 0x001f);
874 phy_write (mii_info, 0x1e, 0x200c);
875 phy_write (mii_info, 0x1d, 0x0005);
876 phy_write (mii_info, 0x1e, 0x0000);
877 phy_write (mii_info, 0x1e, 0x0100);
878 phy_write (mii_info, 0x09, 0x0e00);
879 phy_write (mii_info, 0x04, 0x01e1);
880 phy_write (mii_info, 0x00, 0x9140);
881 phy_write (mii_info, 0x00, 0x1000);
882 udelay (100000);
883 phy_write (mii_info, 0x00, 0x2900);
884 phy_write (mii_info, 0x14, 0x0cd2);
885 phy_write (mii_info, 0x00, 0xa100);
886 phy_write (mii_info, 0x09, 0x0000);
887 phy_write (mii_info, 0x1b, 0x800b);
888 phy_write (mii_info, 0x04, 0x05e1);
889 phy_write (mii_info, 0x00, 0xa100);
890 phy_write (mii_info, 0x00, 0x2100);
891 udelay (1000000);
892 } else if (speed == 10) {
893 phy_write (mii_info, 0x14, 0x8e40);
894 phy_write (mii_info, 0x1b, 0x800b);
895 phy_write (mii_info, 0x14, 0x0c82);
896 phy_write (mii_info, 0x00, 0x8100);
897 udelay (1000000);
898 }
Dave Liu7737d5c2006-11-03 12:11:15 -0600899 }
Kim Phillipsf655ade2008-02-27 15:06:39 -0600900
901 /* handle 88e1111 rev.B2 erratum 5.6 */
902 if (mii_info->autoneg) {
903 status = phy_read (mii_info, PHY_BMCR);
904 phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
905 }
906 /* now the B2 will correctly report autoneg completion status */
Dave Liu7737d5c2006-11-03 12:11:15 -0600907}
908
Heiko Schocher582c55a2010-01-20 09:04:28 +0100909void change_phy_interface_mode (struct eth_device *dev,
Kumar Galaf8c42492010-09-30 09:14:40 -0500910 enum fsl_phy_enet_if type, int speed)
Dave Liu7737d5c2006-11-03 12:11:15 -0600911{
912#ifdef CONFIG_PHY_MODE_NEED_CHANGE
Heiko Schocher582c55a2010-01-20 09:04:28 +0100913 marvell_phy_interface_mode (dev, type, speed);
Dave Liu7737d5c2006-11-03 12:11:15 -0600914#endif
915}