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Stefan Roese7644f162005-09-22 09:16:57 +02001/*
2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
40
Stefan Roese7644f162005-09-22 09:16:57 +020041#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
42
43#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
44
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#undef CONFIG_BOOTARGS
49#undef CONFIG_BOOTCOMMAND
50
51#define CONFIG_PREBOOT /* enable preboot variable */
52
53#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roese7644f162005-09-22 09:16:57 +020055
56#define CONFIG_MII 1 /* MII PHY management */
57#define CONFIG_PHY_ADDR 0 /* PHY address */
58
Jon Loeliger49cf7e82007-07-05 19:52:35 -050059/*
Jon Loeliger11799432007-07-10 09:02:57 -050060 * BOOTP options
61 */
62#define CONFIG_BOOTP_BOOTFILESIZE
63#define CONFIG_BOOTP_BOOTPATH
64#define CONFIG_BOOTP_GATEWAY
65#define CONFIG_BOOTP_HOSTNAME
66
67
68/*
Jon Loeliger49cf7e82007-07-05 19:52:35 -050069 * Command line configuration.
70 */
71#include <config_cmd_default.h>
Stefan Roese7644f162005-09-22 09:16:57 +020072
Jon Loeliger49cf7e82007-07-05 19:52:35 -050073#define CONFIG_CMD_PCI
74#define CONFIG_CMD_IRQ
75#define CONFIG_CMD_ELF
76#define CONFIG_CMD_I2C
77#define CONFIG_CMD_BSP
78#define CONFIG_CMD_EEPROM
79
80#undef CONFIG_CMD_NET
Wolfgang Denkee8028b2010-11-21 20:55:42 +010081#undef CONFIG_CMD_NFS
Stefan Roese7644f162005-09-22 09:16:57 +020082
83#undef CONFIG_WATCHDOG /* watchdog disabled */
84
85#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
86
87/*
88 * Miscellaneous configurable options
89 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_LONGHELP /* undef to save memory */
91#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Stefan Roese7644f162005-09-22 09:16:57 +020092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Stefan Roese7644f162005-09-22 09:16:57 +020094
Jon Loeliger49cf7e82007-07-05 19:52:35 -050095#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese7644f162005-09-22 09:16:57 +020097#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese7644f162005-09-22 09:16:57 +020099#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
101#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
102#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese7644f162005-09-22 09:16:57 +0200103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
Stefan Roese7644f162005-09-22 09:16:57 +0200105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
Stefan Roese7644f162005-09-22 09:16:57 +0200107
108#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
111#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roese7644f162005-09-22 09:16:57 +0200112
Stefan Roese550650d2010-09-20 16:05:31 +0200113#define CONFIG_CONS_INDEX 2 /* Use UART1 */
114#define CONFIG_SYS_NS16550
115#define CONFIG_SYS_NS16550_SERIAL
116#define CONFIG_SYS_NS16550_REG_SIZE 1
117#define CONFIG_SYS_NS16550_CLK get_serial_clock()
118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_BASE_BAUD 691200
Stefan Roese7644f162005-09-22 09:16:57 +0200121
122/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roese7644f162005-09-22 09:16:57 +0200124 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
125 57600, 115200, 230400, 460800, 921600 }
126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
128#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roese7644f162005-09-22 09:16:57 +0200129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roese7644f162005-09-22 09:16:57 +0200131
132#define CONFIG_LOOPW 1 /* enable loopw command */
133
134#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
135
136#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
Stefan Roese7644f162005-09-22 09:16:57 +0200139
140/*-----------------------------------------------------------------------
141 * PCI stuff
142 *-----------------------------------------------------------------------
143 */
144#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
145#define PCI_HOST_FORCE 1 /* configure as pci host */
146#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
147
148#define CONFIG_PCI /* include pci support */
149#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
150#define CONFIG_PCI_PNP /* do pci plug-and-play */
151 /* resource configuration */
152
153#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
154
155#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
156
157#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
160#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */
161#define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
Stefan Roese2076d0a2006-01-18 20:03:15 +0100162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
164#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
165#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
166#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */
167#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
168#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
Stefan Roese7644f162005-09-22 09:16:57 +0200169
170/*-----------------------------------------------------------------------
171 * Start addresses for the final memory configuration
172 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Stefan Roese7644f162005-09-22 09:16:57 +0200174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_SDRAM_BASE 0x00000000
176#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
177#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
178#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
179#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
Stefan Roese7644f162005-09-22 09:16:57 +0200180
181/*
182 * For booting Linux, the board info and command line data
183 * have to be in the first 8 MB of memory, since this is
184 * the maximum mapped by the Linux kernel during initialization.
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese7644f162005-09-22 09:16:57 +0200187/*-----------------------------------------------------------------------
188 * FLASH organization
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
191#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Stefan Roese7644f162005-09-22 09:16:57 +0200192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
194#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese7644f162005-09-22 09:16:57 +0200195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
197#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
198#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
Stefan Roese7644f162005-09-22 09:16:57 +0200199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
201#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
202#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
Stefan Roese7644f162005-09-22 09:16:57 +0200203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese7644f162005-09-22 09:16:57 +0200205
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200206#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200207#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
208#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
Stefan Roese7644f162005-09-22 09:16:57 +0200209
210/*-----------------------------------------------------------------------
211 * I2C EEPROM (CAT24WC16) for environment
212 */
213#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200214#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
216#define CONFIG_SYS_I2C_SLAVE 0x7F
Stefan Roese7644f162005-09-22 09:16:57 +0200217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
219#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roese7644f162005-09-22 09:16:57 +0200220/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
222#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
Stefan Roese7644f162005-09-22 09:16:57 +0200223 /* 16 byte page write mode using*/
224 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Stefan Roese7644f162005-09-22 09:16:57 +0200226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_EEPROM_WREN 1
Stefan Roese7644f162005-09-22 09:16:57 +0200228
Stefan Roese7644f162005-09-22 09:16:57 +0200229/*
230 * Init Memory Controller:
231 *
232 * BR0/1 and OR0/1 (FLASH)
233 */
234#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
235#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
236
237/*-----------------------------------------------------------------------
238 * External Bus Controller (EBC) Setup
239 */
240
241/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_EBC_PB0AP 0x92015480
243#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
Stefan Roese7644f162005-09-22 09:16:57 +0200244
245/* Memory Bank 2 (PB0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
247#define CONFIG_SYS_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese7644f162005-09-22 09:16:57 +0200248
249/* Memory Bank 3 (PB1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
251#define CONFIG_SYS_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese7644f162005-09-22 09:16:57 +0200252
253/*-----------------------------------------------------------------------
254 * Definitions for initial stack pointer and data area (in data cache)
255 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
Stefan Roese7644f162005-09-22 09:16:57 +0200257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200259#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200260#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese7644f162005-09-22 09:16:57 +0200262
263/*-----------------------------------------------------------------------
264 * GPIO definitions
265 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */
267#define CONFIG_SYS_SELF_RST (0x80000000 >> 14) /* GPIO14 */
268#define CONFIG_SYS_PB_LED (0x80000000 >> 16) /* GPIO16 */
269#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */
Stefan Roese7644f162005-09-22 09:16:57 +0200270
Stefan Roese7644f162005-09-22 09:16:57 +0200271#endif /* __CONFIG_H */