Lokesh Vutla | e091832 | 2018-08-27 15:57:13 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * K3: ARM64 MMU setup |
| 4 | * |
Suman Anna | 7873e9d | 2020-08-17 18:15:09 -0500 | [diff] [blame] | 5 | * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/ |
Lokesh Vutla | e091832 | 2018-08-27 15:57:13 +0530 | [diff] [blame] | 6 | * Lokesh Vutla <lokeshvutla@ti.com> |
Suman Anna | 7873e9d | 2020-08-17 18:15:09 -0500 | [diff] [blame] | 7 | * Suman Anna <s-anna@ti.com> |
Michal Simek | 274ccb5 | 2019-01-17 08:22:43 +0100 | [diff] [blame] | 8 | * (This file is derived from arch/arm/mach-zynqmp/cpu.c) |
Lokesh Vutla | e091832 | 2018-08-27 15:57:13 +0530 | [diff] [blame] | 9 | * |
| 10 | */ |
| 11 | |
| 12 | #include <common.h> |
| 13 | #include <asm/system.h> |
| 14 | #include <asm/armv8/mmu.h> |
| 15 | |
Suman Anna | 5bc22e3 | 2019-06-13 10:29:48 +0530 | [diff] [blame] | 16 | #ifdef CONFIG_SOC_K3_AM6 |
Lokesh Vutla | e091832 | 2018-08-27 15:57:13 +0530 | [diff] [blame] | 17 | /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ |
Suman Anna | 60bdc6b | 2019-09-04 16:01:49 +0530 | [diff] [blame] | 18 | #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) |
Lokesh Vutla | e091832 | 2018-08-27 15:57:13 +0530 | [diff] [blame] | 19 | |
| 20 | /* ToDo: Add 64bit IO */ |
| 21 | struct mm_region am654_mem_map[NR_MMU_REGIONS] = { |
| 22 | { |
| 23 | .virt = 0x0UL, |
| 24 | .phys = 0x0UL, |
| 25 | .size = 0x80000000UL, |
| 26 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 27 | PTE_BLOCK_NON_SHARE | |
| 28 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 29 | }, { |
| 30 | .virt = 0x80000000UL, |
| 31 | .phys = 0x80000000UL, |
Suman Anna | 60bdc6b | 2019-09-04 16:01:49 +0530 | [diff] [blame] | 32 | .size = 0x20000000UL, |
| 33 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 34 | PTE_BLOCK_INNER_SHARE |
| 35 | }, { |
| 36 | .virt = 0xa0000000UL, |
| 37 | .phys = 0xa0000000UL, |
| 38 | .size = 0x02100000UL, |
| 39 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | |
| 40 | PTE_BLOCK_INNER_SHARE |
| 41 | }, { |
| 42 | .virt = 0xa2100000UL, |
| 43 | .phys = 0xa2100000UL, |
| 44 | .size = 0x5df00000UL, |
Lokesh Vutla | e091832 | 2018-08-27 15:57:13 +0530 | [diff] [blame] | 45 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 46 | PTE_BLOCK_INNER_SHARE |
| 47 | }, { |
| 48 | .virt = 0x880000000UL, |
| 49 | .phys = 0x880000000UL, |
| 50 | .size = 0x80000000UL, |
| 51 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 52 | PTE_BLOCK_INNER_SHARE |
| 53 | }, { |
Vignesh Raghavendra | 8915a40 | 2020-02-04 11:09:49 +0530 | [diff] [blame] | 54 | .virt = 0x500000000UL, |
| 55 | .phys = 0x500000000UL, |
| 56 | .size = 0x400000000UL, |
| 57 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 58 | PTE_BLOCK_NON_SHARE | |
| 59 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 60 | }, { |
Lokesh Vutla | e091832 | 2018-08-27 15:57:13 +0530 | [diff] [blame] | 61 | /* List terminator */ |
| 62 | 0, |
| 63 | } |
| 64 | }; |
| 65 | |
| 66 | struct mm_region *mem_map = am654_mem_map; |
Suman Anna | 5bc22e3 | 2019-06-13 10:29:48 +0530 | [diff] [blame] | 67 | #endif /* CONFIG_SOC_K3_AM6 */ |
| 68 | |
| 69 | #ifdef CONFIG_SOC_K3_J721E |
Suman Anna | 7873e9d | 2020-08-17 18:15:09 -0500 | [diff] [blame] | 70 | |
| 71 | #ifdef CONFIG_TARGET_J721E_A72_EVM |
Suman Anna | 5bc22e3 | 2019-06-13 10:29:48 +0530 | [diff] [blame] | 72 | /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ |
Suman Anna | 8f4109e | 2020-03-10 16:05:55 -0500 | [diff] [blame] | 73 | #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6) |
Suman Anna | 5bc22e3 | 2019-06-13 10:29:48 +0530 | [diff] [blame] | 74 | |
| 75 | /* ToDo: Add 64bit IO */ |
| 76 | struct mm_region j721e_mem_map[NR_MMU_REGIONS] = { |
| 77 | { |
| 78 | .virt = 0x0UL, |
| 79 | .phys = 0x0UL, |
| 80 | .size = 0x80000000UL, |
| 81 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 82 | PTE_BLOCK_NON_SHARE | |
| 83 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 84 | }, { |
| 85 | .virt = 0x80000000UL, |
| 86 | .phys = 0x80000000UL, |
| 87 | .size = 0x20000000UL, |
| 88 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 89 | PTE_BLOCK_INNER_SHARE |
| 90 | }, { |
| 91 | .virt = 0xa0000000UL, |
| 92 | .phys = 0xa0000000UL, |
Kedar Chitnis | 8bdd83e | 2019-09-04 16:01:50 +0530 | [diff] [blame] | 93 | .size = 0x1bc00000UL, |
Suman Anna | 5bc22e3 | 2019-06-13 10:29:48 +0530 | [diff] [blame] | 94 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | |
| 95 | PTE_BLOCK_NON_SHARE |
| 96 | }, { |
Kedar Chitnis | 8bdd83e | 2019-09-04 16:01:50 +0530 | [diff] [blame] | 97 | .virt = 0xbbc00000UL, |
| 98 | .phys = 0xbbc00000UL, |
| 99 | .size = 0x44400000UL, |
Suman Anna | 5bc22e3 | 2019-06-13 10:29:48 +0530 | [diff] [blame] | 100 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 101 | PTE_BLOCK_INNER_SHARE |
| 102 | }, { |
| 103 | .virt = 0x880000000UL, |
| 104 | .phys = 0x880000000UL, |
| 105 | .size = 0x80000000UL, |
| 106 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 107 | PTE_BLOCK_INNER_SHARE |
| 108 | }, { |
| 109 | .virt = 0x500000000UL, |
| 110 | .phys = 0x500000000UL, |
| 111 | .size = 0x400000000UL, |
| 112 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 113 | PTE_BLOCK_NON_SHARE | |
| 114 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 115 | }, { |
Suman Anna | 8f4109e | 2020-03-10 16:05:55 -0500 | [diff] [blame] | 116 | .virt = 0x4d80000000UL, |
| 117 | .phys = 0x4d80000000UL, |
| 118 | .size = 0x0002000000UL, |
| 119 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | |
| 120 | PTE_BLOCK_INNER_SHARE |
| 121 | }, { |
Suman Anna | 5bc22e3 | 2019-06-13 10:29:48 +0530 | [diff] [blame] | 122 | /* List terminator */ |
| 123 | 0, |
| 124 | } |
| 125 | }; |
| 126 | |
| 127 | struct mm_region *mem_map = j721e_mem_map; |
Suman Anna | 7873e9d | 2020-08-17 18:15:09 -0500 | [diff] [blame] | 128 | #endif /* CONFIG_TARGET_J721E_A72_EVM */ |
| 129 | |
| 130 | #ifdef CONFIG_TARGET_J7200_A72_EVM |
| 131 | #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) |
| 132 | |
| 133 | /* ToDo: Add 64bit IO */ |
| 134 | struct mm_region j7200_mem_map[NR_MMU_REGIONS] = { |
| 135 | { |
| 136 | .virt = 0x0UL, |
| 137 | .phys = 0x0UL, |
| 138 | .size = 0x80000000UL, |
| 139 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 140 | PTE_BLOCK_NON_SHARE | |
| 141 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 142 | }, { |
| 143 | .virt = 0x80000000UL, |
| 144 | .phys = 0x80000000UL, |
| 145 | .size = 0x20000000UL, |
| 146 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 147 | PTE_BLOCK_INNER_SHARE |
| 148 | }, { |
| 149 | .virt = 0xa0000000UL, |
| 150 | .phys = 0xa0000000UL, |
| 151 | .size = 0x04800000UL, |
| 152 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | |
| 153 | PTE_BLOCK_NON_SHARE |
| 154 | }, { |
| 155 | .virt = 0xa4800000UL, |
| 156 | .phys = 0xa4800000UL, |
| 157 | .size = 0x5b800000UL, |
| 158 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 159 | PTE_BLOCK_INNER_SHARE |
| 160 | }, { |
| 161 | .virt = 0x880000000UL, |
| 162 | .phys = 0x880000000UL, |
| 163 | .size = 0x80000000UL, |
| 164 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 165 | PTE_BLOCK_INNER_SHARE |
| 166 | }, { |
| 167 | .virt = 0x500000000UL, |
| 168 | .phys = 0x500000000UL, |
| 169 | .size = 0x400000000UL, |
| 170 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 171 | PTE_BLOCK_NON_SHARE | |
| 172 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 173 | }, { |
| 174 | /* List terminator */ |
| 175 | 0, |
| 176 | } |
| 177 | }; |
| 178 | |
| 179 | struct mm_region *mem_map = j7200_mem_map; |
| 180 | #endif /* CONFIG_TARGET_J7200_A72_EVM */ |
| 181 | |
Suman Anna | 5bc22e3 | 2019-06-13 10:29:48 +0530 | [diff] [blame] | 182 | #endif /* CONFIG_SOC_K3_J721E */ |