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Aubrey.Li3f0606a2007-03-09 13:38:44 +08001/*
Bin Menga1875592016-02-05 19:30:11 -08002 * U-Boot - Configuration file for BF533 EZKIT board
Aubrey.Li3f0606a2007-03-09 13:38:44 +08003 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF533_EZKIT_H__
6#define __CONFIG_BF533_EZKIT_H__
Aubrey.Li3f0606a2007-03-09 13:38:44 +08007
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05009
Mike Frysingercf6f4692008-06-01 09:09:48 -040010/*
11 * Processor Settings
12 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050013#define CONFIG_BFIN_CPU bf533-0.3
Mike Frysingercf6f4692008-06-01 09:09:48 -040014#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
Aubrey.Li3f0606a2007-03-09 13:38:44 +080015
Mike Frysingercf6f4692008-06-01 09:09:48 -040016/*
17 * Clock Settings
18 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
19 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
20 */
21/* CONFIG_CLKIN_HZ is any value in Hz */
22#define CONFIG_CLKIN_HZ 27000000
23/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
24/* 1 = CLKIN / 2 */
25#define CONFIG_CLKIN_HALF 0
26/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
27/* 1 = bypass PLL */
28#define CONFIG_PLL_BYPASS 0
29/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
30/* Values can range from 0-63 (where 0 means 64) */
31#define CONFIG_VCO_MULT 22
32/* CCLK_DIV controls the core clock divider */
33/* Values can be 1, 2, 4, or 8 ONLY */
34#define CONFIG_CCLK_DIV 1
35/* SCLK_DIV controls the system clock divider */
36/* Values can range from 1-15 */
37#define CONFIG_SCLK_DIV 5
38
Mike Frysingercf6f4692008-06-01 09:09:48 -040039/*
40 * Memory Settings
41 */
42#define CONFIG_MEM_SIZE 32
43/* Early EZKITs had 32megs, but later have 64megs */
44#if (CONFIG_MEM_SIZE == 64)
45# define CONFIG_MEM_ADD_WDTH 10
46#else
47# define CONFIG_MEM_ADD_WDTH 9
48#endif
49
50#define CONFIG_EBIU_SDRRC_VAL 0x398
51#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
52
53#define CONFIG_EBIU_AMGCTL_VAL 0xFF
54#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
55#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
56
57#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
58#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
59
Mike Frysingercf6f4692008-06-01 09:09:48 -040060/*
61 * Network Settings
62 */
63#define ADI_CMDS_NETWORK 1
Ben Warren7194ab82009-10-04 22:37:03 -070064#define CONFIG_SMC91111 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +080065#define CONFIG_SMC91111_BASE 0x20310300
Mike Frysingercf6f4692008-06-01 09:09:48 -040066#define SMC91111_EEPROM_INIT() \
67 do { \
Ben Warren7194ab82009-10-04 22:37:03 -070068 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
69 bfin_write_FIO_FLAG_C(PF1); \
70 bfin_write_FIO_FLAG_S(PF0); \
Mike Frysingercf6f4692008-06-01 09:09:48 -040071 SSYNC(); \
72 } while (0)
73#define CONFIG_HOSTNAME bf533-ezkit
Aubrey.Li3f0606a2007-03-09 13:38:44 +080074
Jon Loeligerba2351f2007-07-04 22:31:49 -050075/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040076 * Flash Settings
Jon Loeliger079a1362007-07-10 10:12:10 -050077 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040079#define CONFIG_SYS_MAX_FLASH_BANKS 3
80#define CONFIG_SYS_MAX_FLASH_SECT 40
81#define CONFIG_ENV_IS_IN_FLASH
Mike Frysinger4c5f3072009-09-21 18:04:49 -040082#define CONFIG_ENV_ADDR 0x20030000
Mike Frysingercf6f4692008-06-01 09:09:48 -040083#define CONFIG_ENV_SECT_SIZE 0x10000
Aubrey.Li3f0606a2007-03-09 13:38:44 +080084#define FLASH_TOT_SECT 40
Mike Frysingercf6f4692008-06-01 09:09:48 -040085
Aubrey.Li3f0606a2007-03-09 13:38:44 +080086/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040087 * I2C Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080088 */
Heiko Schocherea818db2013-01-29 08:53:15 +010089#define CONFIG_SYS_I2C_SOFT
90#ifdef CONFIG_SYS_I2C_SOFT
91#define CONFIG_SYS_I2C
Mike Frysingerbeb60e72010-06-08 16:22:44 -040092#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
93#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
Heiko Schocherea818db2013-01-29 08:53:15 +010094#define CONFIG_SYS_I2C_SOFT_SPEED 50000
95#define CONFIG_SYS_I2C_SOFT_SLAVE 0
96#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
97#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +080098
Mike Frysingercf6f4692008-06-01 09:09:48 -040099/*
100 * Misc Settings
101 */
102#define CONFIG_MISC_INIT_R
103#define CONFIG_RTC_BFIN
104#define CONFIG_UART_CONSOLE 0
Mike Frysingercf6f4692008-06-01 09:09:48 -0400105
106/*
107 * Pull in common ADI header for remaining command/environment setup
108 */
109#include <configs/bfin_adi_common.h>
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800110
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800111#endif