Sandeep Sheriker Mallikarjun | f99e0ad | 2019-09-27 13:08:45 +0000 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC. |
| 4 | * |
| 5 | * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries |
| 6 | * |
| 7 | * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com> |
| 8 | */ |
| 9 | |
| 10 | #include "skeleton.dtsi" |
| 11 | #include <dt-bindings/dma/at91.h> |
| 12 | #include <dt-bindings/pinctrl/at91.h> |
| 13 | #include <dt-bindings/interrupt-controller/irq.h> |
| 14 | #include <dt-bindings/gpio/gpio.h> |
| 15 | #include <dt-bindings/clock/at91.h> |
| 16 | |
| 17 | /{ |
| 18 | model = "Microchip SAM9X60 SoC"; |
| 19 | compatible = "microchip,sam9x60"; |
| 20 | |
| 21 | aliases { |
| 22 | serial0 = &dbgu; |
| 23 | gpio0 = &pioA; |
| 24 | gpio1 = &pioB; |
| 25 | }; |
| 26 | |
| 27 | clocks { |
| 28 | slow_xtal: slow_xtal { |
| 29 | compatible = "fixed-clock"; |
| 30 | #clock-cells = <0>; |
| 31 | clock-frequency = <0>; |
| 32 | }; |
| 33 | |
| 34 | main_xtal: main_xtal { |
| 35 | compatible = "fixed-clock"; |
| 36 | #clock-cells = <0>; |
| 37 | clock-frequency = <0>; |
| 38 | }; |
| 39 | }; |
| 40 | |
| 41 | ahb { |
| 42 | compatible = "simple-bus"; |
| 43 | #address-cells = <1>; |
| 44 | #size-cells = <1>; |
| 45 | ranges; |
| 46 | |
| 47 | sdhci0: sdhci-host@80000000 { |
| 48 | compatible = "microchip,sam9x60-sdhci"; |
| 49 | reg = <0x80000000 0x300>; |
| 50 | clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>; |
| 51 | clock-names = "hclock", "multclk", "baseclk"; |
| 52 | bus-width = <4>; |
| 53 | pinctrl-names = "default"; |
| 54 | pinctrl-0 = <&pinctrl_sdhci0>; |
| 55 | }; |
| 56 | |
| 57 | apb { |
| 58 | compatible = "simple-bus"; |
| 59 | #address-cells = <1>; |
| 60 | #size-cells = <1>; |
| 61 | ranges; |
| 62 | |
| 63 | dbgu: serial@fffff200 { |
| 64 | compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; |
| 65 | reg = <0xfffff200 0x200>; |
| 66 | pinctrl-names = "default"; |
| 67 | pinctrl-0 = <&pinctrl_dbgu>; |
| 68 | clocks = <&dbgu_clk>; |
| 69 | clock-names = "usart"; |
| 70 | }; |
| 71 | |
| 72 | pinctrl { |
| 73 | #address-cells = <1>; |
| 74 | #size-cells = <1>; |
| 75 | compatible = "microchip,sam9x60-pinctrl", "simple-bus"; |
| 76 | ranges = <0xfffff400 0xfffff400 0x800>; |
| 77 | reg = <0xfffff400 0x200 /* pioA */ |
| 78 | 0xfffff600 0x200 /* pioB */ |
| 79 | 0xfffff800 0x200 /* pioC */ |
| 80 | 0xfffffa00 0x200>; /* pioD */ |
| 81 | |
| 82 | /* shared pinctrl settings */ |
| 83 | dbgu { |
| 84 | pinctrl_dbgu: dbgu-0 { |
| 85 | atmel,pins = |
| 86 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP |
| 87 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| 88 | }; |
| 89 | }; |
| 90 | |
| 91 | sdhci0 { |
| 92 | pinctrl_sdhci0: sdhci0 { |
| 93 | atmel,pins = |
| 94 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK periph A with pullup */ |
| 95 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 CMD periph A with pullup */ |
| 96 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA15 DAT0 periph A */ |
| 97 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 DAT1 periph A with pullup */ |
| 98 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 DAT2 periph A with pullup */ |
| 99 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 DAT3 periph A with pullup */ |
| 100 | }; |
| 101 | }; |
| 102 | }; |
| 103 | |
| 104 | pioA: gpio@fffff400 { |
| 105 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 106 | reg = <0xfffff400 0x200>; |
| 107 | #gpio-cells = <2>; |
| 108 | gpio-controller; |
| 109 | clocks = <&pioA_clk>; |
| 110 | }; |
| 111 | |
| 112 | pioB: gpio@fffff600 { |
| 113 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 114 | reg = <0xfffff600 0x200>; |
| 115 | #gpio-cells = <2>; |
| 116 | gpio-controller; |
| 117 | clocks = <&pioB_clk>; |
| 118 | }; |
| 119 | |
| 120 | pmc: pmc@fffffc00 { |
| 121 | compatible = "atmel,at91sam9x5-pmc"; |
| 122 | reg = <0xfffffc00 0x200>; |
| 123 | #address-cells = <1>; |
| 124 | #size-cells = <0>; |
| 125 | |
| 126 | main: mainck { |
| 127 | compatible = "atmel,at91sam9x5-clk-main"; |
| 128 | #clock-cells = <0>; |
| 129 | }; |
| 130 | |
| 131 | plla: pllack { |
| 132 | compatible = "microchip,sam9x60-clk-pll"; |
| 133 | #clock-cells = <0>; |
| 134 | clocks = <&main>; |
| 135 | reg = <0>; |
| 136 | atmel,clk-input-range = <8000000 24000000>; |
| 137 | #atmel,pll-clk-output-range-cells = <4>; |
| 138 | atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>; |
| 139 | }; |
| 140 | |
| 141 | mck: masterck { |
| 142 | compatible = "atmel,at91sam9x5-clk-master"; |
| 143 | #clock-cells = <0>; |
| 144 | clocks = <&md_slck>, <&main>, <&plla>; |
| 145 | atmel,clk-output-range = <140000000 200000000>; |
| 146 | atmel,clk-divisors = <1 2 4 6>; |
| 147 | }; |
| 148 | |
| 149 | periph: periphck { |
| 150 | compatible = "microchip,sam9x60-clk-peripheral"; |
| 151 | #address-cells = <1>; |
| 152 | #size-cells = <0>; |
| 153 | clocks = <&mck>; |
| 154 | |
| 155 | pioA_clk: pioA_clk { |
| 156 | #clock-cells = <0>; |
| 157 | reg = <2>; |
| 158 | }; |
| 159 | |
| 160 | pioB_clk: pioB_clk { |
| 161 | #clock-cells = <0>; |
| 162 | reg = <3>; |
| 163 | }; |
| 164 | |
| 165 | sdhci0_clk: sdhci0_clk { |
| 166 | #clock-cells = <0>; |
| 167 | reg = <12>; |
| 168 | }; |
| 169 | |
| 170 | dbgu_clk: dbgu_clk { |
| 171 | #clock-cells = <0>; |
| 172 | reg = <47>; |
| 173 | }; |
| 174 | }; |
| 175 | |
| 176 | generic: gck { |
| 177 | compatible = "microchip,sam9x60-clk-generated"; |
| 178 | #address-cells = <1>; |
| 179 | #size-cells = <0>; |
| 180 | clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>, <&plla>; |
| 181 | |
| 182 | sdhci0_gclk: sdhci0_gclk { |
| 183 | #clock-cells = <0>; |
| 184 | reg = <12>; |
| 185 | }; |
| 186 | }; |
| 187 | }; |
| 188 | |
| 189 | pit: timer@fffffe40 { |
| 190 | compatible = "atmel,at91sam9260-pit"; |
| 191 | reg = <0xfffffe40 0x10>; |
| 192 | clocks = <&mck>; |
| 193 | }; |
| 194 | |
| 195 | slowckc: sckc@fffffe50 { |
| 196 | compatible = "atmel,at91sam9x5-sckc"; |
| 197 | reg = <0xfffffe50 0x4>; |
| 198 | |
| 199 | slow_osc: slow_osc { |
| 200 | compatible = "atmel,at91sam9x5-clk-slow-osc"; |
| 201 | #clock-cells = <0>; |
| 202 | clocks = <&slow_xtal>; |
| 203 | }; |
| 204 | |
| 205 | slow_rc_osc: slow_rc_osc { |
| 206 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; |
| 207 | #clock-cells = <0>; |
| 208 | clock-frequency = <32768>; |
| 209 | }; |
| 210 | |
| 211 | td_slck: td_slck { |
| 212 | compatible = "atmel,at91sam9x5-clk-slow"; |
| 213 | #clock-cells = <0>; |
| 214 | clocks = <&slow_rc_osc>, <&slow_osc>; |
| 215 | }; |
| 216 | |
| 217 | md_slck: md_slck { |
| 218 | compatible = "atmel,at91sam9x5-clk-slow"; |
| 219 | #clock-cells = <0>; |
| 220 | clocks = <&slow_rc_osc>; |
| 221 | }; |
| 222 | }; |
| 223 | }; |
| 224 | }; |
| 225 | }; |