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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamadab9a66b62016-02-16 17:03:48 +09002/*
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +09003 * Copyright (C) 2016-2017 Socionext Inc.
Masahiro Yamada4e3d8402016-07-19 21:56:13 +09004 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadab9a66b62016-02-16 17:03:48 +09005 */
6
7#include <common.h>
Simon Glass9d922452017-05-17 17:18:03 -06008#include <dm.h>
Masahiro Yamadab9a66b62016-02-16 17:03:48 +09009#include <linux/bitops.h>
10#include <linux/io.h>
Masahiro Yamadabc82a132016-03-24 22:32:41 +090011#include <linux/sizes.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090012#include <linux/errno.h>
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090013#include <asm/global_data.h>
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090014#include <asm/gpio.h>
Masahiro Yamadae9986a42017-11-25 00:25:34 +090015#include <dt-bindings/gpio/uniphier-gpio.h>
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090016
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090017#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
18#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
19#define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090020
21struct uniphier_gpio_priv {
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090022 void __iomem *regs;
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090023};
24
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090025static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090026{
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090027 unsigned int reg;
28
29 reg = (bank + 1) * 8;
30
31 /*
32 * Unfortunately, the GPIO port registers are not contiguous because
33 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
34 */
35 if (reg >= UNIPHIER_GPIO_IRQ_EN)
36 reg += 0x10;
37
38 return reg;
39}
40
41static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
42 unsigned int *bank, u32 *mask)
43{
44 *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
45 *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
46}
47
48static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
49 unsigned int reg, u32 mask, u32 val)
50{
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090051 u32 tmp;
52
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090053 tmp = readl(priv->regs + reg);
54 tmp &= ~mask;
55 tmp |= mask & val;
56 writel(tmp, priv->regs + reg);
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090057}
58
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090059static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
60 unsigned int reg, u32 mask, u32 val)
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090061{
62 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
63
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090064 if (!mask)
65 return;
66
67 uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
68 mask, val);
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090069}
70
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090071static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset,
72 unsigned int reg, int val)
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090073{
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090074 unsigned int bank;
75 u32 mask;
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090076
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090077 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
78
79 uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090080}
81
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090082static int uniphier_gpio_offset_read(struct udevice *dev,
83 unsigned int offset, unsigned int reg)
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090084{
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090085 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
86 unsigned int bank, reg_offset;
87 u32 mask;
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090088
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090089 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
90 reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
91
92 return !!(readl(priv->regs + reg_offset) & mask);
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090093}
94
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090095static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090096{
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +090097 return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ?
Masahiro Yamadab9a66b62016-02-16 17:03:48 +090098 GPIOF_INPUT : GPIOF_OUTPUT;
99}
100
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +0900101static int uniphier_gpio_direction_input(struct udevice *dev,
102 unsigned int offset)
103{
104 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);
105
106 return 0;
107}
108
109static int uniphier_gpio_direction_output(struct udevice *dev,
110 unsigned int offset, int value)
111{
112 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
113 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0);
114
115 return 0;
116}
117
118static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset)
119{
120 return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA);
121}
122
123static int uniphier_gpio_set_value(struct udevice *dev,
124 unsigned int offset, int value)
125{
126 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
127
128 return 0;
129}
130
Masahiro Yamadab9a66b62016-02-16 17:03:48 +0900131static const struct dm_gpio_ops uniphier_gpio_ops = {
132 .direction_input = uniphier_gpio_direction_input,
133 .direction_output = uniphier_gpio_direction_output,
134 .get_value = uniphier_gpio_get_value,
135 .set_value = uniphier_gpio_set_value,
136 .get_function = uniphier_gpio_get_function,
137};
138
139static int uniphier_gpio_probe(struct udevice *dev)
140{
141 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
142 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Masahiro Yamadab9a66b62016-02-16 17:03:48 +0900143 fdt_addr_t addr;
Masahiro Yamadab9a66b62016-02-16 17:03:48 +0900144
Masahiro Yamada25484932020-07-17 14:36:48 +0900145 addr = dev_read_addr(dev);
Masahiro Yamadab9a66b62016-02-16 17:03:48 +0900146 if (addr == FDT_ADDR_T_NONE)
147 return -EINVAL;
148
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +0900149 priv->regs = devm_ioremap(dev, addr, SZ_512);
150 if (!priv->regs)
Masahiro Yamadab9a66b62016-02-16 17:03:48 +0900151 return -ENOMEM;
152
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +0900153 uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
154 "ngpios", 0);
Masahiro Yamadab9a66b62016-02-16 17:03:48 +0900155
156 return 0;
157}
158
Masahiro Yamadab9a66b62016-02-16 17:03:48 +0900159static const struct udevice_id uniphier_gpio_match[] = {
160 { .compatible = "socionext,uniphier-gpio" },
161 { /* sentinel */ }
162};
163
164U_BOOT_DRIVER(uniphier_gpio) = {
Masahiro Yamadac5fb1c22017-10-13 19:21:51 +0900165 .name = "uniphier-gpio",
Masahiro Yamadab9a66b62016-02-16 17:03:48 +0900166 .id = UCLASS_GPIO,
167 .of_match = uniphier_gpio_match,
168 .probe = uniphier_gpio_probe,
Masahiro Yamadab9a66b62016-02-16 17:03:48 +0900169 .priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
170 .ops = &uniphier_gpio_ops,
171};