blob: f18f002bea188677b34ac3b2ee603e6a4cc17185 [file] [log] [blame]
Wenyou Yang9e5935c2016-07-20 17:55:12 +08001/*
2 * Copyright (C) 2016 Atmel Corporation
3 * Wenyou.Yang <wenyou.yang@atmel.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <clk-uclass.h>
Simon Glass9d922452017-05-17 17:18:03 -060010#include <dm.h>
Wenyou Yang9e5935c2016-07-20 17:55:12 +080011
12static int at91_slow_clk_enable(struct clk *clk)
13{
14 return 0;
15}
16
17static ulong at91_slow_clk_get_rate(struct clk *clk)
18{
19 return CONFIG_SYS_AT91_SLOW_CLOCK;
20}
21
22static struct clk_ops at91_slow_clk_ops = {
23 .enable = at91_slow_clk_enable,
24 .get_rate = at91_slow_clk_get_rate,
25};
26
27static const struct udevice_id at91_slow_clk_match[] = {
28 { .compatible = "atmel,at91sam9x5-clk-slow" },
29 {}
30};
31
32U_BOOT_DRIVER(at91_slow_clk) = {
33 .name = "at91-slow-clk",
34 .id = UCLASS_CLK,
35 .of_match = at91_slow_clk_match,
36 .ops = &at91_slow_clk_ops,
37};