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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * MOUSSE/MPC8240 Board definitions.
3 * For more info, see http://www.vooha.com/
4 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * (C) Copyright 2001
9 * James Dougherty (jfd@cs.stanford.edu)
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +000012 */
13
14#ifndef __MOUSSE_H
15#define __MOUSSE_H
16
17/* System addresses */
18
19#define PCI_SPECIAL_BASE 0xfe000000
20#define PCI_SPECIAL_SIZE 0x01000000
21
22/* PORTX Device Addresses for Mousse */
23
24#define PORTX_DEV_BASE 0xff000000
25#define PORTX_DEV_SIZE 0x01000000
26
27#define ENET_DEV_BASE 0x80000000
28
29#define PLD_REG_BASE (PORTX_DEV_BASE | 0xe09000)
30#define PLD_REG(off) (*(volatile unsigned char *) \
31 (PLD_REG_BASE + (off)))
32
33#define PLD_REVID_B1 0x7f
34#define PLD_REVID_B2 0x01
35
36/* MPLD */
37#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
38#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f)
39#define SYS_LED_OFF() (PLD_REG(1) |= 0x80)
40#define SYS_LED_ON() (PLD_REG(1) &= ~0x80)
41#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80)
42#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80)
43#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80)
44#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80)
45
46/* SGS M48T59Y */
47#define TOD_BASE (PORTX_DEV_BASE | 0xe0a000)
48#define TOD_REG_BASE (TOD_BASE | 0x1ff0)
49#define TOD_NVRAM_BASE TOD_BASE
50#define TOD_NVRAM_SIZE 0x1ff0
51#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
52
53/* NS16552 SIO */
54#define SERIAL_BASE(_x) (PORTX_DEV_BASE | 0xe08000 | ((_x) ? 0 : 0x80))
55#define N_SIO_CHANNELS 2
56#define N_COM_PORTS N_SIO_CHANNELS
57
58/*
59 * On-board Dec21143 PCI Ethernet
60 * Note: The PCI MBAR chosen here was used from MPC8240UM which states
61 * that PCI memory is at: 0x80000 - 0xFDFFFFFF, if AMBOR[CPU_FD_ALIAS]
62 * is set, then PCI memory maps 1-1 with this address range in the
63 * correct byte order.
64 */
65#define PCI_ENET_IOADDR 0x80000000
66#define PCI_ENET_MEMADDR 0x80000000
67
68/*
69 * Flash Memory Layout
70 *
71 * 2 MB Flash Bank 0 runs in 8-bit mode. In Flash Bank 0, the 32 kB
72 * sector SA3 is obscured by the 32 kB serial/TOD access space, and
73 * the 64 kB sectors SA19-SA26 are obscured by the 512 kB PLCC
74 * containing the fixed boot ROM. (If the 512 kB PLCC is
75 * deconfigured by jumper, this window to Flash Bank 0 becomes
76 * visible, but it still contains the fixed boot code and should be
77 * considered read-only). Flash Bank 0 sectors SA0 (16 kB), SA1 (8
78 * kB), and SA2 (8 kB) are currently unused.
79 *
80 * 2 MB Flash Bank 1 runs in 16-bit mode. Flash Bank 1 is fully
81 * usable, but it's a 16-bit wide device on a 64-bit bus. Therefore
82 * 16-bit words only exist at addresses that are multiples of 8. All
83 * PROM data and control addresses must be multiplied by 8.
84 *
85 * See flashMap.c for description of flash filesystem layout.
86 */
87
88/*
89 * FLASH memory address space: 8-bit wide FLASH memory spaces.
90 */
91#define FLASH0_SEG0_START 0xffe00000 /* Baby 32Kb segment */
92#define FLASH0_SEG0_END 0xffe07fff /* 16 kB + 8 kB + 8 kB */
93#define FLASH0_SEG0_SIZE 0x00008000 /* (sectors SA0-SA2) */
94
95#define FLASH0_SEG1_START 0xffe10000 /* 1MB - 64Kb FLASH0 seg */
96#define FLASH0_SEG1_END 0xffefffff /* 960 kB */
97#define FLASH0_SEG1_SIZE 0x000f0000
98
99#define FLASH0_SEG2_START 0xfff00000 /* Boot Loader stored here */
100#define FLASH0_SEG2_END 0xfff7ffff /* 512 kB FLASH0/PLCC seg */
101#define FLASH0_SEG2_SIZE 0x00080000
102
103#define FLASH0_SEG3_START 0xfff80000 /* 512 kB FLASH0 seg */
104#define FLASH0_SEG3_END 0xffffffff
105#define FLASH0_SEG3_SIZE 0x00080000
106
107/* Where Kahlua starts */
108#define FLASH_RESET_VECT 0xfff00100
109
110/*
111 * CHRP / PREP (MAP A/B) definitions.
112 */
113
114#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */
115#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */
116/* MPC107 (MPC8240 internal EUMBBAR mapped) */
117#define CHRP_REG_ADDR 0xfec00000 /* MPC106 Config, Map B */
118#define CHRP_REG_DATA 0xfee00000 /* MPC106 Config, Map B */
119
120/*
121 * Mousse PCI IDSEL Assignments (Device Number)
122 */
123#define MOUSSE_IDSEL_ENET 13 /* On-board 21143 Ethernet */
124#define MOUSSE_IDSEL_LPCI 14 /* On-board PCI slot */
125#define MOUSSE_IDSEL_82371 15 /* That other thing */
126#define MOUSSE_IDSEL_CPCI2 31 /* CPCI slot 2 */
127#define MOUSSE_IDSEL_CPCI3 30 /* CPCI slot 3 */
128#define MOUSSE_IDSEL_CPCI4 29 /* CPCI slot 4 */
129#define MOUSSE_IDSEL_CPCI5 28 /* CPCI slot 5 */
130#define MOUSSE_IDSEL_CPCI6 27 /* CPCI slot 6 */
131
132/*
133 * Mousse Interrupt Mapping:
134 *
135 * IRQ1 Enet (intA|intB|intC|intD)
136 * IRQ2 CPCI intA (See below)
137 * IRQ3 Local PCI slot intA|intB|intC|intD
138 * IRQ4 COM1 Serial port (Actually higher addressed port on duart)
139 *
140 * PCI Interrupt Mapping in CPCI chassis:
141 *
142 * | CPCI Slot
143 * | 1 (CPU) 2 3 4 5 6
144 * -----------+--------+-------+-------+-------+-------+-------+
145 * intA | X X X
146 * intB | X X X
147 * intC | X X X
148 * intD | X X X
149 */
150
151
152#define EPIC_VECTOR_EXT0 0
153#define EPIC_VECTOR_EXT1 1
154#define EPIC_VECTOR_EXT2 2
155#define EPIC_VECTOR_EXT3 3
156#define EPIC_VECTOR_EXT4 4
157#define EPIC_VECTOR_TM0 16
158#define EPIC_VECTOR_TM1 17
159#define EPIC_VECTOR_TM2 18
160#define EPIC_VECTOR_TM3 19
161#define EPIC_VECTOR_I2C 20
162#define EPIC_VECTOR_DMA0 21
163#define EPIC_VECTOR_DMA1 22
164#define EPIC_VECTOR_I2O 23
165
166
167#define INT_VEC_IRQ0 0
168#define INT_NUM_IRQ0 INT_VEC_IRQ0
169#define MOUSSE_IRQ_ENET EPIC_VECTOR_EXT1 /* Hardwired */
170#define MOUSSE_IRQ_CPCI EPIC_VECTOR_EXT2 /* Hardwired */
171#define MOUSSE_IRQ_LPCI EPIC_VECTOR_EXT3 /* Hardwired */
172#define MOUSSE_IRQ_DUART EPIC_VECTOR_EXT4 /* Hardwired */
173
174/* Onboard DEC 21143 Ethernet */
175#define PCI_ENET_MEMADDR 0x80000000
176#define PCI_ENET_IOADDR 0x80000000
177
178/* Some other PCI device */
179#define PCI_SLOT_MEMADDR 0x81000000
180#define PCI_SLOT_IOADDR 0x81000000
181
182/* Promise ATA66 PCI Device (ATA controller) */
183#define PROMISE_MBAR0 0xa0000000
184#define PROMISE_MBAR1 (PROMISE_MBAR0 + 0x1000)
185#define PROMISE_MBAR2 (PROMISE_MBAR0 + 0x2000)
186#define PROMISE_MBAR3 (PROMISE_MBAR0 + 0x3000)
187#define PROMISE_MBAR4 (PROMISE_MBAR0 + 0x4000)
188#define PROMISE_MBAR5 (PROMISE_MBAR0 + 0x5000)
189
190/* ATA/66 Controller offsets */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_ATA_BASE_ADDR PROMISE_MBAR0
192#define CONFIG_SYS_IDE_MAXBUS 2 /* ide0/ide1 */
193#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 2 drives per controller */
194#define CONFIG_SYS_ATA_IDE0_OFFSET 0
195#define CONFIG_SYS_ATA_IDE1_OFFSET 0x3000
wdenkfe8c2802002-11-03 00:38:21 +0000196/*
197 * Definitions for accessing IDE controller registers
198 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_ATA_DATA_OFFSET 0
200#define CONFIG_SYS_ATA_REG_OFFSET 0
201#define CONFIG_SYS_ATA_ALT_OFFSET (0x1000)
wdenkfe8c2802002-11-03 00:38:21 +0000202
203/*
204 * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS
205 * are defined in config.h and Makefile.
206 * All definitions for these constants must be identical.
207 */
208#define ROM_BASE_ADRS 0xfff00000 /* base address of ROM */
209#define ROM_TEXT_ADRS (ROM_BASE_ADRS+0x0100) /* with PC & SP */
210#define ROM_WARM_ADRS (ROM_TEXT_ADRS+0x0004) /* warm reboot entry */
211#define ROM_SIZE 0x00080000 /* 512KB ROM space */
212#define RAM_LOW_ADRS 0x00010000 /* RAM address for vxWorks */
213#define RAM_HIGH_ADRS 0x00c00000 /* RAM address for bootrom */
214
215/*
216 * NVRAM configuration
217 * NVRAM is implemented via the SGS Thomson M48T59Y
218 * 64Kbit (8Kbx8) Timekeeper SRAM.
219 * This 8KB NVRAM also has a TOD. See m48t59y.{h,c} for more information.
220 */
221
222#define NV_RAM_ADRS TOD_NVRAM_BASE
223#define NV_RAM_INTRVL 1
224#define NV_RAM_WR_ENBL SYS_TOD_UNPROTECT()
225#define NV_RAM_WR_DSBL SYS_TOD_PROTECT()
226
227#define NV_OFF_BOOT0 0x0000 /* Boot string 0 (256b) */
228#define NV_OFF_BOOT1 0x0100 /* Boot string 1 (256b) */
229#define NV_OFF_BOOT2 0x0200 /* Boot string 2 (256b)*/
230#define NV_OFF_MACADDR 0x0400 /* 21143 MAC address (6b) */
231#define NV_OFF_ACTIVEBOOT 0x0406 /* Active boot string, 0 to 2 (1b) */
232#define NV_OFF_UNUSED1 0x0407 /* Unused (1b) */
233#define NV_OFF_BINDFIX 0x0408 /* See sysLib.c:sysBindFix() (1b) */
234#define NV_OFF_UNUSED2 0x0409 /* Unused (7b) */
235#define NV_OFF_TIMEZONE 0x0410 /* TIMEZONE env var (64b) */
236#define NV_OFF_VXWORKS_END 0x07FF /* 2047 VxWorks Total */
237#define NV_OFF_U_BOOT 0x0800 /* 2048 U-Boot boot-loader */
238#define NV_OFF_U_BOOT_ADDR (TOD_BASE + NV_OFF_U_BOOT) /* sysaddr*/
239#define NV_U_BOOT_ENV_SIZE 2048 /* 2K - U-Boot Total */
240#define NV_OFF__next_free (NV_U_BOOT_ENVSIZE +1)
241#define NV_RAM_SIZE 8176 /* NVRAM End */
242
243#endif /* __MOUSSE_H */