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Lokesh Vutlaa7551cf2020-08-05 22:44:28 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/ {
7 chosen {
8 stdout-path = "serial2:115200n8";
9 tick-timer = &timer1;
10 };
11
Vignesh Raghavendradb6451e2020-08-07 00:27:01 +053012 aliases {
13 ethernet0 = &cpsw_port1;
Lokesh Vutla6239cc82021-02-01 11:26:41 +053014 i2c0 = &wkup_i2c0;
15 i2c1 = &mcu_i2c0;
16 i2c2 = &mcu_i2c1;
17 i2c3 = &main_i2c0;
Vignesh Raghavendradb6451e2020-08-07 00:27:01 +053018 };
Lokesh Vutlaa7551cf2020-08-05 22:44:28 +053019};
20
Lokesh Vutlaa7551cf2020-08-05 22:44:28 +053021&cbass_main {
22 u-boot,dm-spl;
23};
24
25&main_navss {
26 u-boot,dm-spl;
27};
28
29&cbass_mcu_wakeup {
30 u-boot,dm-spl;
31
32 timer1: timer@40400000 {
33 compatible = "ti,omap5430-timer";
34 reg = <0x0 0x40400000 0x0 0x80>;
35 ti,timer-alwon;
Tero Kristobb318d82021-06-11 11:45:27 +030036 clock-frequency = <250000000>;
Lokesh Vutlaa7551cf2020-08-05 22:44:28 +053037 u-boot,dm-spl;
38 };
Lokesh Vutla6239cc82021-02-01 11:26:41 +053039
40 chipid@43000014 {
41 u-boot,dm-spl;
42 };
Vignesh Raghavendra2af181b2021-06-07 19:47:51 +053043
44 mcu-navss{
45 u-boot,dm-spl;
Vignesh Raghavendra95eca862021-06-14 14:12:39 +053046 #address-cells = <2>;
47 #size-cells = <2>;
Vignesh Raghavendra2af181b2021-06-07 19:47:51 +053048
49 ringacc@2b800000 {
50 reg = <0x0 0x2b800000 0x0 0x400000>,
51 <0x0 0x2b000000 0x0 0x400000>,
52 <0x0 0x28590000 0x0 0x100>,
53 <0x0 0x2a500000 0x0 0x40000>,
54 <0x0 0x28440000 0x0 0x40000>;
55 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
56 u-boot,dm-spl;
57 };
58
59 dma-controller@285c0000 {
60 reg = <0x0 0x285c0000 0x0 0x100>,
61 <0x0 0x284c0000 0x0 0x4000>,
62 <0x0 0x2a800000 0x0 0x40000>,
63 <0x0 0x284a0000 0x0 0x4000>,
64 <0x0 0x2aa00000 0x0 0x40000>,
65 <0x0 0x28400000 0x0 0x2000>;
66 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
67 "tchanrt", "rflow";
68 u-boot,dm-spl;
69 };
70 };
Lokesh Vutlaa7551cf2020-08-05 22:44:28 +053071};
72
73&secure_proxy_main {
74 u-boot,dm-spl;
75};
76
77&dmsc {
78 u-boot,dm-spl;
79 k3_sysreset: sysreset-controller {
80 compatible = "ti,sci-sysreset";
81 u-boot,dm-spl;
82 };
83};
84
85&k3_pds {
86 u-boot,dm-spl;
87};
88
89&k3_clks {
90 u-boot,dm-spl;
91};
92
93&k3_reset {
94 u-boot,dm-spl;
95};
96
97&wkup_pmx0 {
98 u-boot,dm-spl;
99};
100
101&main_pmx0 {
102 u-boot,dm-spl;
103};
104
105&main_uart0 {
106 u-boot,dm-spl;
107};
108
109&mcu_uart0 {
110 u-boot,dm-spl;
111};
112
113&main_sdhci0 {
114 u-boot,dm-spl;
115};
116
117&main_sdhci1 {
118 u-boot,dm-spl;
119};
120
121&wkup_i2c0_pins_default {
122 u-boot,dm-spl;
123};
124
125&wkup_i2c0 {
126 u-boot,dm-spl;
127};
128
129&main_i2c0 {
130 u-boot,dm-spl;
131};
132
133&main_i2c0_pins_default {
134 u-boot,dm-spl;
135};
136
137&exp2 {
138 u-boot,dm-spl;
139};
Vignesh Raghavendra86c9bd42020-08-07 00:26:56 +0530140
Vignesh Raghavendradb6451e2020-08-07 00:27:01 +0530141&mcu_cpsw {
142 reg = <0x0 0x46000000 0x0 0x200000>,
143 <0x0 0x40f00200 0x0 0x8>;
144 reg-names = "cpsw_nuss", "mac_efuse";
Vignesh Raghavendra1e8f2462021-02-09 13:38:48 +0530145 /delete-property/ ranges;
Vignesh Raghavendradb6451e2020-08-07 00:27:01 +0530146
147 cpsw-phy-sel@40f04040 {
148 compatible = "ti,am654-cpsw-phy-sel";
149 reg= <0x0 0x40f04040 0x0 0x4>;
150 reg-names = "gmii-sel";
151 };
152};
153
Vignesh Raghavendra86c9bd42020-08-07 00:26:56 +0530154&main_usbss0_pins_default {
155 u-boot,dm-spl;
156};
157
158&usbss0 {
159 u-boot,dm-spl;
160 ti,usb2-only;
161};
162
163&usb0 {
164 dr_mode = "peripheral";
165 u-boot,dm-spl;
166};
Vignesh Raghavendrac07d0682020-08-13 14:56:17 +0530167
168&wkup_gpio_pins_default {
169 u-boot,dm-spl;
170};
171
Vignesh Raghavendrac07d0682020-08-13 14:56:17 +0530172&mcu_fss0_hpb0_pins_default {
173 u-boot,dm-spl;
174};
175
176&fss {
177 u-boot,dm-spl;
178};
179
180&hbmc {
181 u-boot,dm-spl;
182
183 flash@0,0 {
184 u-boot,dm-spl;
185 };
186};
187
188&hbmc_mux {
189 u-boot,dm-spl;
190};
Aswath Govindraju08189ff2021-07-21 21:28:43 +0530191
192&serdes_ln_ctrl {
193 u-boot,mux-autoprobe;
194};
195
196&usb_serdes_mux {
197 u-boot,mux-autoprobe;
198};
199
200&serdes0 {
201 u-boot,dm-spl;
202};