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Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721E SoC Family
4 *
Lokesh Vutla70e16742021-02-01 11:26:40 +05305 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +05306 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/pinctrl/k3.h>
11#include <dt-bindings/soc/ti,sci_pm_domain.h>
12
13/ {
14 model = "Texas Instruments K3 J721E SoC";
15 compatible = "ti,j721e";
16 interrupt-parent = <&gic500>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 serial0 = &wkup_uart0;
22 serial1 = &mcu_uart0;
23 serial2 = &main_uart0;
24 serial3 = &main_uart1;
25 serial4 = &main_uart2;
26 serial5 = &main_uart3;
27 serial6 = &main_uart4;
28 serial7 = &main_uart5;
29 serial8 = &main_uart6;
30 serial9 = &main_uart7;
31 serial10 = &main_uart8;
32 serial11 = &main_uart9;
Lokesh Vutla70e16742021-02-01 11:26:40 +053033 ethernet0 = &cpsw_port1;
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +053034 };
35
36 chosen { };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41 cpu-map {
42 cluster0: cluster0 {
43 core0 {
44 cpu = <&cpu0>;
45 };
46
47 core1 {
48 cpu = <&cpu1>;
49 };
50 };
51
52 };
53
54 cpu0: cpu@0 {
55 compatible = "arm,cortex-a72";
56 reg = <0x000>;
57 device_type = "cpu";
58 enable-method = "psci";
59 i-cache-size = <0xC000>;
60 i-cache-line-size = <64>;
61 i-cache-sets = <256>;
62 d-cache-size = <0x8000>;
63 d-cache-line-size = <64>;
64 d-cache-sets = <128>;
65 next-level-cache = <&L2_0>;
66 };
67
68 cpu1: cpu@1 {
69 compatible = "arm,cortex-a72";
70 reg = <0x001>;
71 device_type = "cpu";
72 enable-method = "psci";
73 i-cache-size = <0xC000>;
74 i-cache-line-size = <64>;
75 i-cache-sets = <256>;
76 d-cache-size = <0x8000>;
77 d-cache-line-size = <64>;
78 d-cache-sets = <128>;
79 next-level-cache = <&L2_0>;
80 };
81 };
82
83 L2_0: l2-cache0 {
84 compatible = "cache";
85 cache-level = <2>;
86 cache-size = <0x100000>;
87 cache-line-size = <64>;
88 cache-sets = <2048>;
89 next-level-cache = <&msmc_l3>;
90 };
91
92 msmc_l3: l3-cache0 {
93 compatible = "cache";
94 cache-level = <3>;
95 };
96
97 firmware {
98 optee {
99 compatible = "linaro,optee-tz";
100 method = "smc";
101 };
102
103 psci: psci {
104 compatible = "arm,psci-1.0";
105 method = "smc";
106 };
107 };
108
109 a72_timer0: timer-cl0-cpu0 {
110 compatible = "arm,armv8-timer";
111 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
112 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
113 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
114 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
115 };
116
117 pmu: pmu {
Tom Rinifa09b122021-09-10 17:37:43 -0400118 compatible = "arm,cortex-a72-pmu";
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530119 /* Recommendation from GIC500 TRM Table A.3 */
120 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
121 };
122
Suman Annaf3f20182020-07-24 17:51:40 -0500123 cbass_main: bus@100000 {
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530124 compatible = "simple-bus";
125 #address-cells = <2>;
126 #size-cells = <2>;
127 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
128 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530129 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
Lokesh Vutla70e16742021-02-01 11:26:40 +0530130 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
131 <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
132 <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530133 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
Lokesh Vutla70e16742021-02-01 11:26:40 +0530134 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
135 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
136 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530137 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
138 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
Lokesh Vutla70e16742021-02-01 11:26:40 +0530139 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
140 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530141 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
142 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
143 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
Lokesh Vutla70e16742021-02-01 11:26:40 +0530144 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
145
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530146 /* MCUSS_WKUP Range */
147 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
148 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
149 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
150 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
151 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
152 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
153 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
154 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
155 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
156 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
157 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530158 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
159 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
160
Suman Annaf3f20182020-07-24 17:51:40 -0500161 cbass_mcu_wakeup: bus@28380000 {
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530162 compatible = "simple-bus";
163 #address-cells = <2>;
164 #size-cells = <2>;
165 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
166 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
167 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
168 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
169 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
170 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
171 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
172 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
173 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
174 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
175 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
176 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
177 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
178 };
179 };
180};
181
182/* Now include the peripherals for each bus segments */
183#include "k3-j721e-main.dtsi"
184#include "k3-j721e-mcu-wakeup.dtsi"