blob: eca1f9dd82720406b9f20a8111132d0e66593663 [file] [log] [blame]
Stefan Roese46499132009-10-27 16:11:26 +01001/*
2 * Copyright 2007-2009 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include "config.h" /* CONFIG_BOARDDIR */
24
25#ifndef RESET_VECTOR_ADDRESS
26#define RESET_VECTOR_ADDRESS 0xfffffffc
27#endif
28
29OUTPUT_ARCH(powerpc)
30/* Do we need any of these for elf?
31 __DYNAMIC = 0; */
32PHDRS
33{
34 text PT_LOAD;
35 bss PT_LOAD;
36}
37
38SECTIONS
39{
40 /* Read-only sections, merged into text segment: */
41 . = + SIZEOF_HEADERS;
42 .interp : { *(.interp) }
43 .hash : { *(.hash) }
44 .dynsym : { *(.dynsym) }
45 .dynstr : { *(.dynstr) }
46 .rel.text : { *(.rel.text) }
47 .rela.text : { *(.rela.text) }
48 .rel.data : { *(.rel.data) }
49 .rela.data : { *(.rela.data) }
50 .rel.rodata : { *(.rel.rodata) }
51 .rela.rodata : { *(.rela.rodata) }
52 .rel.got : { *(.rel.got) }
53 .rela.got : { *(.rela.got) }
54 .rel.ctors : { *(.rel.ctors) }
55 .rela.ctors : { *(.rela.ctors) }
56 .rel.dtors : { *(.rel.dtors) }
57 .rela.dtors : { *(.rela.dtors) }
58 .rel.bss : { *(.rel.bss) }
59 .rela.bss : { *(.rela.bss) }
60 .rel.plt : { *(.rel.plt) }
61 .rela.plt : { *(.rela.plt) }
62 .init : { *(.init) }
63 .plt : { *(.plt) }
64 .text :
65 {
66 *(.text)
67 *(.got1)
68 } :text
69 _etext = .;
70 PROVIDE (etext = .);
71 .rodata :
72 {
73 *(.eh_frame)
74 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
75 } :text
76 .fini : { *(.fini) } =0
77 .ctors : { *(.ctors) }
78 .dtors : { *(.dtors) }
79
80 /* Read-write section, merged into data segment: */
81 . = (. + 0x00FF) & 0xFFFFFF00;
82 _erotext = .;
83 PROVIDE (erotext = .);
84 .reloc :
85 {
86 *(.got)
87 _GOT2_TABLE_ = .;
88 *(.got2)
89 _FIXUP_TABLE_ = .;
90 *(.fixup)
91 }
92 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
93 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
94
95 .data :
96 {
97 *(.data)
98 *(.data1)
99 *(.sdata)
100 *(.sdata2)
101 *(.dynamic)
102 CONSTRUCTORS
103 }
104 _edata = .;
105 PROVIDE (edata = .);
106
107 . = .;
108 __u_boot_cmd_start = .;
109 .u_boot_cmd : { *(.u_boot_cmd) }
110 __u_boot_cmd_end = .;
111
112 . = .;
113 __start___ex_table = .;
114 __ex_table : { *(__ex_table) }
115 __stop___ex_table = .;
116
117 . = ALIGN(256);
118 __init_begin = .;
119 .text.init : { *(.text.init) }
120 .data.init : { *(.data.init) }
121 . = ALIGN(256);
122 __init_end = .;
123
124#ifdef CONFIG_440
125 .bootpg RESET_VECTOR_ADDRESS - 0xffc :
126 {
Stefan Roesea47a12b2010-04-15 16:07:28 +0200127 arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
Stefan Roese46499132009-10-27 16:11:26 +0100128
129 /*
130 * PPC440 board need a board specific object with the
131 * TLB definitions. This needs to get included right after
132 * start.o, since the first shadow TLB only covers 4k
133 * of address space.
134 */
135 CONFIG_BOARDDIR/init.o (.bootpg)
136 } :text = 0xffff
137#endif
138
139 .resetvec RESET_VECTOR_ADDRESS :
140 {
141 *(.resetvec)
142 } :text = 0xffff
143
144 . = RESET_VECTOR_ADDRESS + 0x4;
145
146 /*
147 * Make sure that the bss segment isn't linked at 0x0, otherwise its
148 * address won't be updated during relocation fixups. Note that
149 * this is a temporary fix. Code to dynamically the fixup the bss
150 * location will be added in the future. When the bss relocation
151 * fixup code is present this workaround should be removed.
152 */
153#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
154 . |= 0x10;
155#endif
156
157 __bss_start = .;
158 .bss (NOLOAD) :
159 {
160 *(.sbss) *(.scommon)
161 *(.dynbss)
162 *(.bss)
163 *(COMMON)
164 } :bss
165
166 . = ALIGN(4);
167 _end = . ;
168 PROVIDE (end = .);
169}