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wdenk12f34242003-09-02 22:48:03 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
wdenk12f34242003-09-02 22:48:03 +000031#ifndef __ASSEMBLY__
32#include <galileo/core.h>
33#endif
34
35#include "../board/evb64260/local.h"
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41
42#define CONFIG_P3G4 1 /* this is a P3G4 board */
43#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */
44
45#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
46
47#undef CONFIG_ECC /* enable ECC support */
48/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
49
50/* which initialization functions to call for this board */
51#define CONFIG_MISC_INIT_R 1
wdenkc837dcb2004-01-20 23:12:12 +000052#define CONFIG_BOARD_EARLY_INIT_F 1
wdenk12f34242003-09-02 22:48:03 +000053
54#define CFG_BOARD_NAME "P3G4"
55
56#undef CFG_HUSH_PARSER
57#define CFG_PROMPT_HUSH_PS2 "> "
58
59/*
60 * The following defines let you select what serial you want to use
61 * for your console driver.
62 *
63 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
64 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
65 */
66#define CONFIG_MPSC
stroesedcb2f952005-05-03 06:06:41 +000067#define CONFIG_MPSC_PORT 0
wdenk12f34242003-09-02 22:48:03 +000068
69#define CONFIG_NET_MULTI /* attempt all available adapters */
70
71/* define this if you want to enable GT MAC filtering */
72#define CONFIG_GT_USE_MAC_HASH_TABLE
73
74#undef CONFIG_ETHER_PORT_MII /* use RMII */
75
stroesedcb2f952005-05-03 06:06:41 +000076#if 0
wdenk12f34242003-09-02 22:48:03 +000077#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
78#else
79#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
80#endif
81#define CONFIG_ZERO_BOOTDELAY_CHECK
82
stroesedcb2f952005-05-03 06:06:41 +000083#define CONFIG_PREBOOT "echo;" \
84 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
85 "echo"
86
wdenk12f34242003-09-02 22:48:03 +000087#undef CONFIG_BOOTARGS
stroesedcb2f952005-05-03 06:06:41 +000088
89#define CONFIG_EXTRA_ENV_SETTINGS \
90 "netdev=eth0\0" \
91 "hostname=p3g4\0" \
92 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010093 "nfsroot=${serverip}:${rootpath}\0" \
stroesedcb2f952005-05-03 06:06:41 +000094 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010095 "addip=setenv bootargs ${bootargs} " \
96 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
97 ":${hostname}:${netdev}:off panic=1\0" \
98 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
stroesedcb2f952005-05-03 06:06:41 +000099 "flash_nfs=run nfsargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100100 "bootm ${kernel_addr}\0" \
stroesedcb2f952005-05-03 06:06:41 +0000101 "flash_self=run ramargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100102 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
103 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
stroesedcb2f952005-05-03 06:06:41 +0000104 "bootm\0" \
105 "rootpath=/opt/eldk/ppc_74xx\0" \
106 "bootfile=/tftpboot/p3g4/uImage\0" \
107 "kernel_addr=ff000000\0" \
108 "ramdisk_addr=ff010000\0" \
109 "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \
110 "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100111 "cp.b 100000 fff00000 ${filesize};" \
stroesedcb2f952005-05-03 06:06:41 +0000112 "setenv filesize;saveenv\0" \
113 "upd=run load;run update\0" \
114 ""
115#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk12f34242003-09-02 22:48:03 +0000116
117#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
118#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
119
120#undef CONFIG_WATCHDOG /* watchdog disabled */
121#undef CONFIG_ALTIVEC /* undef to disable */
122
123#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
124 CONFIG_BOOTP_BOOTFILESIZE)
125
wdenk149dded2003-09-10 18:20:28 +0000126#define CONFIG_TIMESTAMP /* Print image info with timestamp */
wdenk12f34242003-09-02 22:48:03 +0000127
stroesedcb2f952005-05-03 06:06:41 +0000128#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
129 CFG_CMD_ASKENV | \
130 CFG_CMD_DHCP | \
131 CFG_CMD_PCI | \
132 CFG_CMD_ELF | \
133 CFG_CMD_MII | \
134 CFG_CMD_PING | \
135 CFG_CMD_UNIVERSE| \
136 CFG_CMD_BSP )
wdenk12f34242003-09-02 22:48:03 +0000137
138/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
139#include <cmd_confdefs.h>
140
141/*
142 * Miscellaneous configurable options
143 */
144#define CFG_LONGHELP /* undef to save memory */
145#define CFG_PROMPT "=> " /* Monitor Command Prompt */
146#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
147#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
148#else
149#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
150#endif
151#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
152#define CFG_MAXARGS 16 /* max number of command args */
153#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
154
155#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
156#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
157
158#define CFG_LOAD_ADDR 0x00300000 /* default load address */
159
160#define CFG_HZ 1000 /* decr freq: 1ms ticks */
161#define CFG_BUS_HZ 133000000 /* 133 MHz */
162#define CFG_BUS_CLK CFG_BUS_HZ
163
164#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
165
166
167/*
168 * Low Level Configuration Settings
169 * (address mappings, register initial values, etc.)
170 * You should know what you are doing if you make changes here.
171 */
172
173/*-----------------------------------------------------------------------
174 * Definitions for initial stack pointer and data area
175 */
176#define CFG_INIT_RAM_ADDR 0x40000000
177#define CFG_INIT_RAM_END 0x1000
178#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
179#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
180#define CFG_INIT_RAM_LOCK
181
182
183/*-----------------------------------------------------------------------
184 * Start addresses for the final memory configuration
185 * (Set up by the startup code)
186 * Please note that CFG_SDRAM_BASE _must_ start at 0
187 */
188#define CFG_SDRAM_BASE 0x00000000
wdenk2d5b5612003-10-14 19:43:55 +0000189#define CFG_FLASH_BASE 0xff000000
wdenk12f34242003-09-02 22:48:03 +0000190#define CFG_RESET_ADDRESS 0xfff00100
191#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
192#define CFG_MONITOR_BASE TEXT_BASE
193#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
194
195/* areas to map different things with the GT in physical space */
196#define CFG_DRAM_BANKS 1
197#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
198
199/* What to put in the bats. */
200#define CFG_MISC_REGION_BASE 0xf0000000
201
202/* Peripheral Device section */
203#define CFG_GT_REGS 0xf8000000
204#define CFG_DEV_BASE 0xff000000
205
206#define CFG_DEV0_SPACE CFG_DEV_BASE
207#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE)
208#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE)
209#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE)
210
211#define CFG_DEV0_SIZE _8M /* Flash bank */
212#define CFG_DEV1_SIZE 0 /* unused */
213#define CFG_DEV2_SIZE 0 /* unused */
214#define CFG_DEV3_SIZE 0 /* unused */
215
216#define CFG_16BIT_BOOT_PAR 0xc01b5e7c
217#define CFG_DEV0_PAR CFG_16BIT_BOOT_PAR
218
219#if 0 /* Wrong?? NTL */
220#define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
221 /* DMAAck[1:0] GNT0[1:0] */
222#else
223#define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
224 /* REQ0[1:0] GNT0[1:0] */
225#endif
226#define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
227 /* DMAReq[4] DMAAck[4] WDNMI WDE */
228#if 0 /* Wrong?? NTL */
229#define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
230 /* DMAAck[1:0] GNT1[1:0] */
231#else
232#define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
233 /* GPP[22] (RS232IntB or PCI1Int) */
234 /* GPP[21] (RS323IntA) */
235 /* BClkIn */
236 /* REQ1[1:0] GNT1[1:0] */
237#endif
238
239#if 0 /* Wrong?? NTL */
240# define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
241 /* GPP[27:26] Int[1:0] */
242#else
243# define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
244 /* GPP[29] (PCI1Int) */
245 /* BClkOut0 */
246 /* GPP[27] (PCI0Int) */
247 /* GPP[26] (RtcInt or PCI1Int) */
248 /* CPUInt[25:24] */
249#endif
250
251#define CFG_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
252
253#if 0 /* Wrong?? - NTL */
254# define CFG_GPP_LEVEL_CONTROL 0x000002c6
255#else
256# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
257 /* gpp[29] */
258 /* gpp[27:26] */
259 /* gpp[22:21] */
260
261# define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
262 /* idmas use buffer 1,1
263 comm use buffer 0
264 pci use buffer 1,1
265 cpu use buffer 0
266 normal load (see also ifdef HVL)
267 standard SDRAM (see also ifdef REG)
268 non staggered refresh */
269 /* 31:26 25 23 20 19 18 16 */
270 /* 110110 00 111 0 0 00 1 */
271 /* refresh_count=0x200
272 phisical interleaving disable
273 virtual interleaving enable */
274 /* 15 14 13:0 */
275 /* 1 0 0x200 */
276#endif
277
278#if 0
279#define CFG_DUART_IO CFG_DEV2_SPACE
280#define CFG_DUART_CHAN 1 /* channel to use for console */
281#endif
282#undef CFG_INIT_CHAN1
283#undef CFG_INIT_CHAN2
284#if 0
285#define SRAM_BASE CFG_DEV0_SPACE
286#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
287#endif
288
289
290/*-----------------------------------------------------------------------
291 * PCI stuff
292 *-----------------------------------------------------------------------
293 */
294
295#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
296#define PCI_HOST_FORCE 1 /* configure as pci host */
297#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
298
299#define CONFIG_PCI /* include pci support */
300#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
301#define CONFIG_PCI_PNP /* do pci plug-and-play */
302
303/* PCI MEMORY MAP section */
304#define CFG_PCI0_MEM_BASE 0x80000000
305#define CFG_PCI0_MEM_SIZE _128M
stroesedcb2f952005-05-03 06:06:41 +0000306#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
307
wdenk12f34242003-09-02 22:48:03 +0000308#define CFG_PCI1_MEM_BASE 0x88000000
309#define CFG_PCI1_MEM_SIZE _128M
wdenk12f34242003-09-02 22:48:03 +0000310#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
311
wdenk12f34242003-09-02 22:48:03 +0000312/* PCI I/O MAP section */
313#define CFG_PCI0_IO_BASE 0xfa000000
314#define CFG_PCI0_IO_SIZE _16M
wdenk12f34242003-09-02 22:48:03 +0000315#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
316#define CFG_PCI0_IO_SPACE_PCI 0x00000000
stroesedcb2f952005-05-03 06:06:41 +0000317
318#define CFG_PCI1_IO_BASE 0xfb000000
319#define CFG_PCI1_IO_SIZE _16M
wdenk12f34242003-09-02 22:48:03 +0000320#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
321#define CFG_PCI1_IO_SPACE_PCI 0x00000000
322
323/*----------------------------------------------------------------------
324 * Initial BAT mappings
325 */
326
327/* NOTES:
328 * 1) GUARDED and WRITE_THRU not allowed in IBATS
329 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
330 */
331
332/* SDRAM */
333#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
334#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
335#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
336#define CFG_DBAT0U CFG_IBAT0U
337
338/* init ram */
339#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
340#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
341#define CFG_DBAT1L CFG_IBAT1L
342#define CFG_DBAT1U CFG_IBAT1U
343
344/* PCI0, PCI1 in one BAT */
345#define CFG_IBAT2L BATL_NO_ACCESS
346#define CFG_IBAT2U CFG_DBAT2U
347#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
348#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
349
350/* GT regs, bootrom, all the devices, PCI I/O */
351#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
352#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
353#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
354#define CFG_DBAT3U CFG_IBAT3U
355
356/* I2C speed and slave address (for compatability) defaults */
357#define CFG_I2C_SPEED 400000
358#define CFG_I2C_SLAVE 0x7F
359
360/* I2C addresses for the two DIMM SPD chips */
361#ifndef CONFIG_EVB64260_750CX
362#define DIMM0_I2C_ADDR 0x56
363#define DIMM1_I2C_ADDR 0x54
364#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
365#define DIMM0_I2C_ADDR 0x54
366#define DIMM1_I2C_ADDR 0x54
367#endif
368
369/*
370 * For booting Linux, the board info and command line data
371 * have to be in the first 8 MB of memory, since this is
372 * the maximum mapped by the Linux kernel during initialization.
373 */
374#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
375
376/*-----------------------------------------------------------------------
377 * FLASH organization
378 */
379#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
380#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
381
wdenk2d5b5612003-10-14 19:43:55 +0000382#define CFG_EXTRA_FLASH_DEVICE BOOT_DEVICE
wdenk12f34242003-09-02 22:48:03 +0000383#define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */
384#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */
385
386#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
387#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
388#define CFG_FLASH_CFI 1
389
390#define CFG_ENV_IS_IN_FLASH 1
391#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
392#define CFG_ENV_SECT_SIZE 0x20000
393#define CFG_ENV_ADDR 0xFFFE0000
394
395/*-----------------------------------------------------------------------
396 * Cache Configuration
397 */
398#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
399#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
400#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
401#endif
402
403/*-----------------------------------------------------------------------
404 * L2CR setup -- make sure this is right for your board!
405 * look in include/74xx_7xx.h for the defines used here
406 */
407
408#define CFG_L2
409
410#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
411 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
412
413#define L2_ENABLE (L2_INIT | L2CR_L2E)
414
415/*
416 * Internal Definitions
417 *
418 * Boot Flags
419 */
420#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
421#define BOOTFLAG_WARM 0x02 /* Software reboot */
422
423#define CFG_BOARD_ASM_INIT 1
424
425
426#endif /* __CONFIG_H */