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York Sunf749db32014-06-23 15:15:56 -07001/*
2 * Copyright 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS2_EMU_H
8#define __LS2_EMU_H
9
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053010#include "ls2080a_common.h"
York Sunf749db32014-06-23 15:15:56 -070011
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053012#define CONFIG_IDENT_STRING " LS2080A-EMU"
Bhupesh Sharmabbeeb8b2015-01-06 13:18:58 -080013
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070014#define CONFIG_SYS_CLK_FREQ 100000000
15#define CONFIG_DDR_CLK_FREQ 133333333
16
17#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
18#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
19
York Sunf749db32014-06-23 15:15:56 -070020#define CONFIG_DDR_SPD
21#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
22#define SPD_EEPROM_ADDRESS1 0x51
23#define SPD_EEPROM_ADDRESS2 0x52
York Sund9c68b12014-08-13 10:21:05 -070024#define SPD_EEPROM_ADDRESS3 0x53
York Sunf749db32014-06-23 15:15:56 -070025#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
26#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070027#define CONFIG_DIMM_SLOTS_PER_CTLR 1
28#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053029#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070030#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053031#endif
York Sunf749db32014-06-23 15:15:56 -070032
York Sun4f2532c2015-01-06 13:19:01 -080033#define CONFIG_FSL_DDR_SYNC_REFRESH
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070034
35#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
36#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
37/*
38 * NOR Flash Timing Params
39 */
40#define CONFIG_SYS_NOR0_CSPR \
41 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
42 CSPR_PORT_SIZE_16 | \
43 CSPR_MSEL_NOR | \
44 CSPR_V)
45#define CONFIG_SYS_NOR0_CSPR_EARLY \
46 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
47 CSPR_PORT_SIZE_16 | \
48 CSPR_MSEL_NOR | \
49 CSPR_V)
50#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
51#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
52 FTIM0_NOR_TEADC(0x1) | \
53 FTIM0_NOR_TEAHC(0x1))
54#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
55 FTIM1_NOR_TRAD_NOR(0x1))
56#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
57 FTIM2_NOR_TCH(0x0) | \
58 FTIM2_NOR_TWP(0x1))
59#define CONFIG_SYS_NOR_FTIM3 0x04000000
60#define CONFIG_SYS_IFC_CCR 0x01000000
61
62#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
63#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
64#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
65#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
66#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
67#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
68#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
69#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
70#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
71
72/* Debug Server firmware */
73#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
74#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
75
J. German Rivera125e2bc2015-03-20 19:28:18 -070076/*
77 * This trick allows users to load MC images into DDR directly without
78 * copying from NOR flash. It dramatically improves speed.
79 */
80#define CONFIG_SYS_LS_MC_FW_IN_DDR
81#define CONFIG_SYS_LS_MC_DPL_IN_DDR
82#define CONFIG_SYS_LS_MC_DPC_IN_DDR
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070083
J. German Rivera125e2bc2015-03-20 19:28:18 -070084#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070085
86/* Store environment at top of flash */
87#define CONFIG_ENV_IS_NOWHERE 1
88#define CONFIG_ENV_SIZE 0x1000
89
York Sunf749db32014-06-23 15:15:56 -070090#endif /* __LS2_EMU_H */