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Marek Vasut10da95a2010-07-26 06:30:25 +02001/*
2 * Balloon3 configuration file
3 *
4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Marek Vasut10da95a2010-07-26 06:30:25 +02007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Board Configuration Options
14 */
Marek Vasutabc20ab2011-11-26 07:20:07 +010015#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
Marek Vasut10da95a2010-07-26 06:30:25 +020016#define CONFIG_BALLOON3 1 /* Balloon3 board */
17
18/*
19 * Environment settings
20 */
21#define CONFIG_ENV_OVERWRITE
22#define CONFIG_SYS_MALLOC_LEN (128*1024)
Marek Vasut20ae5192010-10-03 01:05:55 +020023#define CONFIG_ARCH_CPU_INIT
Marek Vasut10da95a2010-07-26 06:30:25 +020024#define CONFIG_BOOTCOMMAND \
Marek Vasut20ae5192010-10-03 01:05:55 +020025 "fpga load 0x0 0x50000 0x62638; " \
Marek Vasut10da95a2010-07-26 06:30:25 +020026 "if usb reset && fatload usb 0 0xa4000000 uImage; then " \
27 "bootm 0xa4000000; " \
28 "fi; " \
Marek Vasut20ae5192010-10-03 01:05:55 +020029 "bootm 0xd0000;"
Marek Vasut10da95a2010-07-26 06:30:25 +020030#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200"
31#define CONFIG_TIMESTAMP
32#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
33#define CONFIG_CMDLINE_TAG
34#define CONFIG_SETUP_MEMORY_TAGS
Marek Vasut20ae5192010-10-03 01:05:55 +020035#define CONFIG_SYS_TEXT_BASE 0x0
Marek Vasut10da95a2010-07-26 06:30:25 +020036#define CONFIG_LZMA /* LZMA compression support */
37
38/*
39 * Serial Console Configuration
40 */
41#define CONFIG_PXA_SERIAL
42#define CONFIG_STUART 1
Marek Vasutce6971c2012-09-12 12:36:25 +020043#define CONFIG_CONS_INDEX 2
Marek Vasut10da95a2010-07-26 06:30:25 +020044#define CONFIG_BAUDRATE 115200
Marek Vasut10da95a2010-07-26 06:30:25 +020045
46/*
47 * Bootloader Components Configuration
48 */
49#include <config_cmd_default.h>
50
51#undef CONFIG_CMD_NET
Sebastien Carlier6d8962e2010-11-05 15:48:07 +010052#undef CONFIG_CMD_NFS
Marek Vasut10da95a2010-07-26 06:30:25 +020053#undef CONFIG_CMD_ENV
54#undef CONFIG_CMD_IMLS
55#define CONFIG_CMD_USB
56#define CONFIG_CMD_FPGA
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +053057#define CONFIG_CMD_FPGA_LOADMK
Marek Vasut10da95a2010-07-26 06:30:25 +020058#undef CONFIG_LCD
59
60/*
61 * KGDB
62 */
63#ifdef CONFIG_CMD_KGDB
64#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
Marek Vasut10da95a2010-07-26 06:30:25 +020065#endif
66
67/*
68 * HUSH Shell Configuration
69 */
70#define CONFIG_SYS_HUSH_PARSER 1
Marek Vasut10da95a2010-07-26 06:30:25 +020071
72#define CONFIG_SYS_LONGHELP
73#ifdef CONFIG_SYS_HUSH_PARSER
74#define CONFIG_SYS_PROMPT "$ "
75#else
Marek Vasut10da95a2010-07-26 06:30:25 +020076#endif
77#define CONFIG_SYS_CBSIZE 256
78#define CONFIG_SYS_PBSIZE \
79 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
80#define CONFIG_SYS_MAXARGS 16
81#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
82#define CONFIG_SYS_DEVICE_NULLDEV 1
83
84/*
85 * Clock Configuration
86 */
87#undef CONFIG_SYS_CLKS_IN_HZ
Marek Vasut10da95a2010-07-26 06:30:25 +020088#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
89
90/*
Marek Vasut10da95a2010-07-26 06:30:25 +020091 * DRAM Map
92 */
93#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */
94#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
95#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
96#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */
97#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
98#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */
99#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */
100
101#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
102#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */
103
104#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
105#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
106
107#define CONFIG_SYS_LOAD_ADDR 0xa1000000
108
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200109#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Marek Vasut20ae5192010-10-03 01:05:55 +0200110#define CONFIG_SYS_INIT_SP_ADDR \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200111 (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200112
Marek Vasut10da95a2010-07-26 06:30:25 +0200113/*
114 * NOR FLASH
115 */
116#ifdef CONFIG_CMD_FLASH
117#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
118#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
119#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
120
121#define CONFIG_SYS_FLASH_CFI
122#define CONFIG_FLASH_CFI_DRIVER 1
123#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
124
125#define CONFIG_SYS_MAX_FLASH_BANKS 1
126#define CONFIG_SYS_MAX_FLASH_SECT 256
127
128#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
129
Marek Vasutf90aea22013-11-04 20:50:21 +0100130#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
131#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
132#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
133#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
Marek Vasut10da95a2010-07-26 06:30:25 +0200134#define CONFIG_SYS_FLASH_PROTECTION
135#define CONFIG_ENV_IS_IN_FLASH
136#else
137#define CONFIG_SYS_NO_FLASH
138#define CONFIG_SYS_ENV_IS_NOWHERE
139#endif
140
141#define CONFIG_SYS_MONITOR_BASE 0x000000
142#define CONFIG_SYS_MONITOR_LEN 0x40000
143
144#define CONFIG_ENV_SIZE 0x2000
145#define CONFIG_ENV_ADDR 0x40000
146#define CONFIG_ENV_SECT_SIZE 0x10000
147
148/*
149 * GPIO settings
150 */
151#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd
152#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e
153#define CONFIG_SYS_GPSR2_VAL 0x7131c000
154#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff
155
156#define CONFIG_SYS_GPCR0_VAL 0x0
157#define CONFIG_SYS_GPCR1_VAL 0x0
158#define CONFIG_SYS_GPCR2_VAL 0x0
159#define CONFIG_SYS_GPCR3_VAL 0x0
160
161#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02
162#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7
163#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff
164#define CONFIG_SYS_GPDR3_VAL 0x000201fe
165
166#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000
167#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b
168#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a
169#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa
170#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
171#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa
172#define CONFIG_SYS_GAFR3_L_VAL 0x54510003
173#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
174
175#define CONFIG_SYS_PSSR_VAL 0x30
176
177/*
178 * Clock settings
179 */
180#define CONFIG_SYS_CKEN 0xffffffff
181#define CONFIG_SYS_CCCR 0x00000290
182
183/*
184 * Memory settings
185 */
186#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8
187#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0
188#define CONFIG_SYS_MSC2_VAL 0x74a42491
189#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3
190#define CONFIG_SYS_MDREFR_VAL 0x001d8018
191#define CONFIG_SYS_MDMRS_VAL 0x00220022
192#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
193#define CONFIG_SYS_SXCNFG_VAL 0x00000000
194#define CONFIG_SYS_MEM_BUF_IMP 0x0f
195
196/*
197 * PCMCIA and CF Interfaces
198 */
199#define CONFIG_SYS_MECR_VAL 0x00000000
200#define CONFIG_SYS_MCMEM0_VAL 0x00014307
201#define CONFIG_SYS_MCMEM1_VAL 0x00014307
202#define CONFIG_SYS_MCATT0_VAL 0x0001c787
203#define CONFIG_SYS_MCATT1_VAL 0x0001c787
204#define CONFIG_SYS_MCIO0_VAL 0x0001430f
205#define CONFIG_SYS_MCIO1_VAL 0x0001430f
206
207/*
208 * LCD
209 */
210#ifdef CONFIG_LCD
211#define CONFIG_BALLOON3LCD
212#define CONFIG_VIDEO_LOGO
213#define CONFIG_CMD_BMP
214#define CONFIG_SPLASH_SCREEN
215#define CONFIG_SPLASH_SCREEN_ALIGN
216#define CONFIG_VIDEO_BMP_GZIP
217#define CONFIG_VIDEO_BMP_RLE8
218#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
219#endif
220
221/*
222 * USB
223 */
224#ifdef CONFIG_CMD_USB
225#define CONFIG_USB_OHCI_NEW
226#define CONFIG_SYS_USB_OHCI_CPU_INIT
227#define CONFIG_SYS_USB_OHCI_BOARD_INIT
228#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
229#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
230#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3"
231#define CONFIG_USB_STORAGE
232#define CONFIG_DOS_PARTITION
233#define CONFIG_CMD_FAT
234#define CONFIG_CMD_EXT2
235#endif
236
237/*
238 * FPGA
239 */
240#ifdef CONFIG_CMD_FPGA
241#define CONFIG_FPGA
242#define CONFIG_FPGA_XILINX
243#define CONFIG_FPGA_SPARTAN3
244#define CONFIG_SYS_FPGA_PROG_FEEDBACK
245#define CONFIG_SYS_FPGA_WAIT 1000
246#define CONFIG_MAX_FPGA_DEVICES 1
247#endif
248
249#endif /* __CONFIG_H */