Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 |
Graeme Russ | dbf7115 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 3 | * Graeme Russ, <graeme.russ@gmail.com> |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 4 | * |
| 5 | * (C) Copyright 2007 |
Graeme Russ | dbf7115 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 6 | * Daniel Hellstrom, Gaisler Research, <daniel@gaisler.com> |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 7 | * |
| 8 | * (C) Copyright 2006 |
Graeme Russ | dbf7115 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 9 | * Detlev Zundel, DENX Software Engineering, <dzu@denx.de> |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 10 | * |
| 11 | * (C) Copyright -2003 |
Graeme Russ | dbf7115 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 12 | * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 13 | * |
| 14 | * (C) Copyright 2002 |
Albert ARIBAUD | fa82f87 | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 15 | * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 16 | * |
| 17 | * (C) Copyright 2001 |
Graeme Russ | dbf7115 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 18 | * Josh Huber, Mission Critical Linux, Inc, <huber@mclx.com> |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 19 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 20 | * SPDX-License-Identifier: GPL-2.0+ |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * This file contains the high-level API for the interrupt sub-system |
Graeme Russ | dbf7115 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 25 | * of the x86 port of U-Boot. Most of the functionality has been |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 26 | * shamelessly stolen from the leon2 / leon3 ports of U-Boot. |
| 27 | * Daniel Hellstrom, Detlev Zundel, Wolfgang Denk and Josh Huber are |
| 28 | * credited for the corresponding work on those ports. The original |
Graeme Russ | dbf7115 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 29 | * interrupt handling routines for the x86 port were written by |
Albert ARIBAUD | fa82f87 | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 30 | * Daniel Engström |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 31 | */ |
| 32 | |
| 33 | #include <common.h> |
| 34 | #include <asm/interrupt.h> |
| 35 | |
Simon Glass | c2bf0df | 2017-01-16 07:04:14 -0700 | [diff] [blame] | 36 | #if !CONFIG_IS_ENABLED(X86_64) |
| 37 | |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 38 | struct irq_action { |
| 39 | interrupt_handler_t *handler; |
| 40 | void *arg; |
| 41 | unsigned int count; |
| 42 | }; |
| 43 | |
Bin Meng | 6c50527 | 2015-10-22 19:13:26 -0700 | [diff] [blame] | 44 | static struct irq_action irq_handlers[SYS_NUM_IRQS] = { {0} }; |
Graeme Russ | 83088af | 2011-11-08 02:33:15 +0000 | [diff] [blame] | 45 | static int spurious_irq_cnt; |
| 46 | static int spurious_irq; |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 47 | |
| 48 | void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg) |
| 49 | { |
| 50 | int status; |
| 51 | |
Bin Meng | 6c50527 | 2015-10-22 19:13:26 -0700 | [diff] [blame] | 52 | if (irq < 0 || irq >= SYS_NUM_IRQS) { |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 53 | printf("irq_install_handler: bad irq number %d\n", irq); |
| 54 | return; |
| 55 | } |
| 56 | |
| 57 | if (irq_handlers[irq].handler != NULL) |
| 58 | printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n", |
Graeme Russ | 83088af | 2011-11-08 02:33:15 +0000 | [diff] [blame] | 59 | (ulong) handler, |
| 60 | (ulong) irq_handlers[irq].handler); |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 61 | |
Graeme Russ | 83088af | 2011-11-08 02:33:15 +0000 | [diff] [blame] | 62 | status = disable_interrupts(); |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 63 | |
Graeme Russ | 1c409bc | 2009-11-24 20:04:21 +1100 | [diff] [blame] | 64 | irq_handlers[irq].handler = handler; |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 65 | irq_handlers[irq].arg = arg; |
| 66 | irq_handlers[irq].count = 0; |
| 67 | |
| 68 | unmask_irq(irq); |
| 69 | |
| 70 | if (status) |
| 71 | enable_interrupts(); |
| 72 | |
| 73 | return; |
| 74 | } |
| 75 | |
| 76 | void irq_free_handler(int irq) |
| 77 | { |
| 78 | int status; |
| 79 | |
Bin Meng | 6c50527 | 2015-10-22 19:13:26 -0700 | [diff] [blame] | 80 | if (irq < 0 || irq >= SYS_NUM_IRQS) { |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 81 | printf("irq_free_handler: bad irq number %d\n", irq); |
| 82 | return; |
| 83 | } |
| 84 | |
Graeme Russ | 83088af | 2011-11-08 02:33:15 +0000 | [diff] [blame] | 85 | status = disable_interrupts(); |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 86 | |
| 87 | mask_irq(irq); |
| 88 | |
| 89 | irq_handlers[irq].handler = NULL; |
| 90 | irq_handlers[irq].arg = NULL; |
| 91 | |
| 92 | if (status) |
| 93 | enable_interrupts(); |
| 94 | |
| 95 | return; |
| 96 | } |
| 97 | |
Graeme Russ | 564a998 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 98 | void do_irq(int hw_irq) |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 99 | { |
Graeme Russ | 564a998 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 100 | int irq = hw_irq - 0x20; |
| 101 | |
Bin Meng | 6c50527 | 2015-10-22 19:13:26 -0700 | [diff] [blame] | 102 | if (irq < 0 || irq >= SYS_NUM_IRQS) { |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 103 | printf("do_irq: bad irq number %d\n", irq); |
| 104 | return; |
| 105 | } |
| 106 | |
| 107 | if (irq_handlers[irq].handler) { |
| 108 | mask_irq(irq); |
| 109 | |
| 110 | irq_handlers[irq].handler(irq_handlers[irq].arg); |
| 111 | irq_handlers[irq].count++; |
| 112 | |
| 113 | unmask_irq(irq); |
| 114 | specific_eoi(irq); |
| 115 | |
| 116 | } else { |
| 117 | if ((irq & 7) != 7) { |
| 118 | spurious_irq_cnt++; |
| 119 | spurious_irq = irq; |
| 120 | } |
| 121 | } |
| 122 | } |
Simon Glass | c2bf0df | 2017-01-16 07:04:14 -0700 | [diff] [blame] | 123 | #endif |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 124 | |
| 125 | #if defined(CONFIG_CMD_IRQ) |
Wolfgang Denk | 54841ab | 2010-06-28 22:00:46 +0200 | [diff] [blame] | 126 | int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 127 | { |
Simon Glass | c2bf0df | 2017-01-16 07:04:14 -0700 | [diff] [blame] | 128 | #if !CONFIG_IS_ENABLED(X86_64) |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 129 | int irq; |
| 130 | |
| 131 | printf("Spurious IRQ: %u, last unknown IRQ: %d\n", |
Graeme Russ | 83088af | 2011-11-08 02:33:15 +0000 | [diff] [blame] | 132 | spurious_irq_cnt, spurious_irq); |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 133 | |
Graeme Russ | 83088af | 2011-11-08 02:33:15 +0000 | [diff] [blame] | 134 | printf("Interrupt-Information:\n"); |
| 135 | printf("Nr Routine Arg Count\n"); |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 136 | |
Bin Meng | 6c50527 | 2015-10-22 19:13:26 -0700 | [diff] [blame] | 137 | for (irq = 0; irq < SYS_NUM_IRQS; irq++) { |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 138 | if (irq_handlers[irq].handler != NULL) { |
Graeme Russ | 83088af | 2011-11-08 02:33:15 +0000 | [diff] [blame] | 139 | printf("%02d %08lx %08lx %d\n", |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 140 | irq, |
| 141 | (ulong)irq_handlers[irq].handler, |
| 142 | (ulong)irq_handlers[irq].arg, |
| 143 | irq_handlers[irq].count); |
| 144 | } |
| 145 | } |
Simon Glass | c2bf0df | 2017-01-16 07:04:14 -0700 | [diff] [blame] | 146 | #endif |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 147 | |
| 148 | return 0; |
| 149 | } |
| 150 | #endif |