| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Stephen Warren | 0d04f34 | 2012-08-05 16:07:22 +0000 | [diff] [blame] | 2 | /* |
| Stephen Warren | fe84ebf | 2016-04-04 20:00:41 -0600 | [diff] [blame] | 3 | * (C) Copyright 2012-2016 Stephen Warren |
| Stephen Warren | 0d04f34 | 2012-08-05 16:07:22 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __CONFIG_H |
| 7 | #define __CONFIG_H |
| 8 | |
| Stephen Warren | fe84ebf | 2016-04-04 20:00:41 -0600 | [diff] [blame] | 9 | #include <linux/sizes.h> |
| 10 | #include <asm/arch/timer.h> |
| Alexander Stein | 060f9bf | 2015-07-24 09:22:11 +0200 | [diff] [blame] | 11 | |
| Matthias Brugger | 8e3361c | 2019-11-19 16:01:03 +0100 | [diff] [blame] | 12 | #ifndef __ASSEMBLY__ |
| 13 | #include <asm/arch/base.h> |
| 14 | #endif |
| 15 | |
| Stephen Warren | fe84ebf | 2016-04-04 20:00:41 -0600 | [diff] [blame] | 16 | /* Use SoC timer for AArch32, but architected timer for AArch64 */ |
| 17 | #ifndef CONFIG_ARM64 |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 18 | #define CFG_SYS_TIMER_RATE 1000000 |
| 19 | #define CFG_SYS_TIMER_COUNTER \ |
| Stephen Warren | fe84ebf | 2016-04-04 20:00:41 -0600 | [diff] [blame] | 20 | (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo) |
| 21 | #endif |
| 22 | |
| Stephen Warren | fe84ebf | 2016-04-04 20:00:41 -0600 | [diff] [blame] | 23 | /* Memory layout */ |
| Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 24 | #define CFG_SYS_SDRAM_BASE 0x00000000 |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 25 | #define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE |
| Stephen Warren | fe84ebf | 2016-04-04 20:00:41 -0600 | [diff] [blame] | 26 | /* |
| 27 | * The board really has 256M. However, the VC (VideoCore co-processor) shares |
| 28 | * the RAM, and uses a configurable portion at the top. We tell U-Boot that a |
| 29 | * smaller amount of RAM is present in order to avoid stomping on the area |
| 30 | * the VC uses. |
| 31 | */ |
| Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 32 | #define CFG_SYS_SDRAM_SIZE SZ_128M |
| Stephen Warren | fe84ebf | 2016-04-04 20:00:41 -0600 | [diff] [blame] | 33 | |
| Stephen Warren | 0d04f34 | 2012-08-05 16:07:22 +0000 | [diff] [blame] | 34 | #endif |