blob: 3b67ea90bccaa9f7bdfaae65e08906b9d65bd102 [file] [log] [blame]
Eric Millbrandt5b53b292009-08-13 10:14:21 -05001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Eric Schumann, Phytec Messatechnik GmbH
7 *
8 * (C) Copyright 2009
9 * Jon Smirl <jonsmirl@gmail.com>
10 *
11 * (C) Copyright 2009
12 * Eric Millbrandt, DEKA Research and Development Corporation
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36#define CONFIG_BOARDINFO "galaxy5200"
37
38/*
39 * High Level Configuration Options
40 * (easy to change)
41 */
42#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
43#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
44#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
45#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
46#define BOOTFLAG_WARM 0x02 /* Software reboot */
47
48/*
49 * Serial console configuration
50 */
51#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */
52 /* define gps port conf. */
53 /* register later on to */
54 /* enable UART function! */
55#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
56#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
57
58/*
59 * Command line configuration.
60 */
61#include <config_cmd_default.h>
62
63#define CONFIG_CMD_DATE
64#define CONFIG_CMD_DHCP
65#define CONFIG_CMD_EEPROM
66#define CONFIG_CMD_I2C
67#define CONFIG_CMD_JFFS2
68#define CONFIG_CMD_MII
69#define CONFIG_CMD_NFS
70#define CONFIG_CMD_SNTP
71#define CONFIG_CMD_PING
72#define CONFIG_CMD_ASKENV
73#define CONFIG_CMD_USB
74#define CONFIG_CMD_CACHE
75#define CONFIG_CMD_FAT
76
77#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
78
79#if (TEXT_BASE == 0xFE000000) /* Boot low */
80#define CONFIG_SYS_LOWBOOT 1
81#endif
82/* RAMBOOT will be defined automatically in memory section */
83
Eric Millbrandt0d042032009-08-25 10:30:26 -050084#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
85#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
Eric Millbrandt5b53b292009-08-13 10:14:21 -050086 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
87
88/*
89 * Autobooting
90 */
91#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
92#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
93 /* even with bootdelay=0 */
94#undef CONFIG_BOOTARGS
95
96#define CONFIG_PREBOOT "echo;" \
Eric Millbrandt0d042032009-08-25 10:30:26 -050097 "echo Welcome to U-Boot;"\
Eric Millbrandt5b53b292009-08-13 10:14:21 -050098 "echo"
99
100/*
101 * IPB Bus clocking configuration.
102 */
103#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
104#define CONFIG_SYS_XLB_PIPELINING 1
105
106/*
107 * I2C configuration
108 */
109#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
110#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
111#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
112#define CONFIG_SYS_I2C_SLAVE 0x7F
Eric Millbrandt5da71ef2009-09-03 08:09:44 -0500113#define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500114
115/*
116 * EEPROM CAT24WC32 configuration
117 */
118#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
119#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
120#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
121#define CONFIG_SYS_EEPROM_SIZE 4096
122#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
123#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
124
125/*
126 * RTC configuration
127 */
128#define RTC
129#define CONFIG_RTC_DS3231 1
130#define CONFIG_SYS_I2C_RTC_ADDR 0x68
131
132/*
133 * Flash configuration
134 */
135
136#define CONFIG_SYS_FLASH_BASE 0xfe000000
137/*
138 * The flash size is autoconfigured, but cpu/mpc5xxx/cpu_init.c needs this
139 * variable defined
140 */
141#define CONFIG_SYS_FLASH_SIZE 0x02000000
142#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
143
144#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
145#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
146#define CONFIG_SYS_FLASH_EMPTY_INFO
147#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */
148#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
149 /* (= chip selects) */
150#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
151
152/*
153 * Use hardware protection. This seems required, as the BDI uses hardware
154 * protection. Without this, U-Boot can't work with this sectors as its
155 * protection is software only by default.
156 */
157#define CONFIG_SYS_FLASH_PROTECTION 1
158
159/*
160 * Environment settings
161 */
162
163#define CONFIG_ENV_IS_IN_EEPROM 1
164#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
165 /* beginning of the EEPROM */
166#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
167
168#define CONFIG_ENV_OVERWRITE 1
169
170/*
171 * SDRAM configuration
172 */
173#define SDRAM_DDR 1
174#define SDRAM_MODE 0x018D0000
175#define SDRAM_EMODE 0x40090000
176#define SDRAM_CONTROL 0x71500F00
177#define SDRAM_CONFIG1 0x73711930
178#define SDRAM_CONFIG2 0x47770000
179
180/*
181 * Memory map
182 */
183#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
184 /* bootloader or debugger config */
185#define CONFIG_SYS_SDRAM_BASE 0x00000000
186#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
187
188/* Use SRAM until RAM will be available */
189#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
190
191/* End of used area in SPRAM */
192#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
193
194/* Size in bytes reserved for initial data */
195#define CONFIG_SYS_GBL_DATA_SIZE 128
196
197#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
198 CONFIG_SYS_GBL_DATA_SIZE)
199#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
200
201#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
202#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
203# define CONFIG_SYS_RAMBOOT 1
204#endif
205
206#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
207#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
208#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
209
210/* Chip Select configuration for NAND flash */
211#define CONFIG_SYS_CS1_START 0x20000000
212#define CONFIG_SYS_CS1_SIZE 0x90000
213#define CONFIG_SYS_CS1_CFG 0x0002d900
214
Eric Millbrandt795d2462009-08-28 07:14:04 -0500215/* Chip Select configuration for Epson S1D13513 */
216#define CONFIG_SYS_CS3_START 0x10000000
217#define CONFIG_SYS_CS3_SIZE 0x400000
218#define CONFIG_SYS_CS3_CFG 0xffff3d10
219
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500220/*
221 * Ethernet configuration
222 */
223#define CONFIG_MPC5xxx_FEC 1
224#define CONFIG_MPC5xxx_FEC_MII100
225#define CONFIG_PHY_ADDR 0x01
226#define CONFIG_NO_AUTOLOAD 1
227
228/*
229 * GPIO configuration
230 *
231 * GPS port configuration
232 *
233 * [29:31] = 01x
234 * AC97 on PSC1
235 * PSC1_0 -> AC97 SDATA out
236 * PSC1_1 -> AC97 SDTA in
237 * PSC1_2 -> AC97 SYNC out
238 * PSC1_3 -> AC97 bitclock out
239 * PSC1_4 -> AC97 reset out
240 *
241 * [28] = Reserved
242 *
243 * [25:27] = 110
244 * SPI on PSC2
245 * PSC2_0 -> MOSI
246 * PSC2_1 -> MISO
247 * PSC2_2 -> n/a
248 * PSC2_3 -> CLK
249 * PSC2_4 -> SS
250 *
251 * [24] = Reserved
252 *
253 * [20:23] = 0001
254 * USB on PSC3
255 * PSC3_0 -> USB_OE OE out
256 * PSC3_1 -> USB_TXN Tx- out
257 * PSC3_2 -> USB_TXP Tx+ out
258 * PSC3_3 -> USB_TXD
259 * PSC3_4 -> USB_RXP Rx+ in
260 * PSC3_5 -> USB_RXN Rx- in
261 * PSC3_6 -> USB_PWR PortPower out
262 * PSC3_7 -> USB_SPEED speed out
263 * PSC3_8 -> USB_SUSPEND suspend
264 * PSC3_9 -> USB_OVRCURNT overcurrent in
265 *
266 * [18:19] = 10
267 * Two UARTs
268 *
269 * [17] = 0
270 * USB differential mode
271 *
272 * [16] = 1
273 * PCI disabled
274 *
275 * [12:15] = 0101
276 * Ethernet 100Mbit with MD
277 * ETH_0 -> ETH Txen
278 * ETH_1 -> ETH TxD0
279 * ETH_2 -> ETH TxD1
280 * ETH_3 -> ETH TxD2
281 * ETH_4 -> ETH TxD3
282 * ETH_5 -> ETH Txerr
283 * ETH_6 -> ETH MDC
284 * ETH_7 -> ETH MDIO
285 * ETH_8 -> ETH RxDv
286 * ETH_9 -> ETH RxCLK
287 * ETH_10 -> ETH Collision
288 * ETH_11 -> ETH TxD
289 * ETH_12 -> ETH RxD0
290 * ETH_13 -> ETH RxD1
291 * ETH_14 -> ETH RxD2
292 * ETH_15 -> ETH RxD3
293 * ETH_16 -> ETH Rxerr
294 * ETH_17 -> ETH CRS
295 *
296 * [9:11] = 111
297 * SPI on PSC6
298 * PSC6_0 -> MISO
299 * PSC6_1 -> SS#
300 * PSC6_2 -> MOSI
301 * PSC6_3 -> CLK
302 *
303 * [8] = 0
304 * IrDA/USB 48MHz clock generated internally
305 *
306 * [6:7] = 01
307 * ATA chip selects on csb_4/5
308 * CSB_4 -> ATA_CS0 out
309 * CSB_5 -> ATA_CS1 out
310 *
311 * [5] = 1
312 * PSC3_4 is used as CS6
313 *
314 * [4] = 1
315 * PSC3_5 is used as CS7
316 *
317 * [2:3] = 00
318 * No Alternatives
319 *
320 * [1] = 0
321 * gpio_wkup_7 is GPIO
322 *
323 * [0] = 0
324 * gpio_wkup_6 is GPIO
325 *
326 */
327#define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162
328
329/*
330 * Miscellaneous configurable options
331 */
332#define CONFIG_SYS_LONGHELP /* undef to save memory */
333#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
334
335#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
336
337#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
338#if defined(CONFIG_CMD_KGDB)
339#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
340#endif
341
342#if defined(CONFIG_CMD_KGDB)
343#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
344#else
345#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
346#endif
347#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
348 /* Print Buffer Size */
349#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
350#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
351
352#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
353#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
354
355#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
356#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
357
358#define CONFIG_DISPLAY_BOARDINFO 1
359
360#define CONFIG_SYS_HUSH_PARSER 1
361#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
362
363#define CONFIG_CRC32_VERIFY 1
364
365#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
366 CONFIG_BOOTP_DNS | \
367 CONFIG_BOOTP_DNS2 | \
368 CONFIG_BOOTP_SEND_HOSTNAME )
369
Eric Millbrandt71ce9bd2009-09-21 11:05:55 -0500370#define CONFIG_VERSION_VARIABLE 1
371
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500372/*
373 * Various low-level settings
374 */
375#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
376#define CONFIG_SYS_HID0_FINAL HID0_ICE
377
378/* no burst access on the LPB */
379#define CONFIG_SYS_CS_BURST 0x00000000
380/* one deadcycle for the 33MHz statemachine */
381#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
382
383#define CONFIG_SYS_BOOTCS_CFG 0x0002d900
384#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
385#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
386
Eric Millbrandt0d042032009-08-25 10:30:26 -0500387#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500388
389/*
390 * USB settings
391 */
392#define CONFIG_USB_CLOCK 0x0001bbbb
393/* USB is on PSC3 */
394#define CONFIG_PSC3_USB
395#define CONFIG_USB_CONFIG 0x00000100
396#define CONFIG_USB_OHCI
397#define CONFIG_USB_STORAGE
398
399/*
400 * IDE/ATA stuff Supports IDE harddisk
401 */
402#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
403#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
404#undef CONFIG_IDE_LED /* LED for ide not supported */
405
406#define CONFIG_IDE_RESET 1 /* reset for ide supported */
407#define CONFIG_IDE_PREINIT
408#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
409#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
410#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
411#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
412/* Offset for data I/O */
413#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
414/* Offset for normal register accesses */
415#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
416/* Offset for alternate registers */
417#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
418/* Interval between registers */
419#define CONFIG_SYS_ATA_STRIDE 4
420#define CONFIG_ATAPI 1
421
422/* we enable IDE and FAT support, so we also need partition support */
423#define CONFIG_DOS_PARTITION 1
424
425/*
426 * Open Firmware flat tree
427 */
428#define CONFIG_OF_LIBFDT 1
429#define CONFIG_OF_BOARD_SETUP 1
430
431#define OF_CPU "PowerPC,5200@0"
432#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
433#define OF_SOC "soc5200@f0000000"
434#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2600"
435
436#endif /* __CONFIG_H */