blob: e194c8f7bbed64eaef0204657262f8740e523233 [file] [log] [blame]
Stefan Roesee53b5072009-06-09 11:50:40 +02001/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009, DAVE Srl <www.dave.eu>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com
24 *
25 */
26
27/*
28 * MECP5123 board configuration file
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34#define CONFIG_MECP5123 1
35/*
36 * Memory map for the MECP5123 board:
37 *
38 * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB)
39 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
40 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
41 * 0x8200_0000 - 0x8200_FFFF VPC-3 (64 KB)
42 * 0xFFC0_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
43 */
44
45/*
46 * High Level Configuration Options
47 */
48#define CONFIG_E300 1 /* E300 Family */
49#define CONFIG_MPC512X 1 /* MPC512X family */
50
51#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
52
53#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
54#define CONFIG_MISC_INIT_R
55
56#define CONFIG_SYS_IMMR 0x80000000
57#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
58
59#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
60#define CONFIG_SYS_MEMTEST_END 0x00400000
61
62/*
63 * DDR Setup - manually set all parameters as there's no SPD etc.
64 */
65#define CONFIG_SYS_DDR_SIZE 512 /* MB */
66
67#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
68#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
69
70/* DDR Controller Configuration
71 *
72 * SYS_CFG:
73 * [31:31] MDDRC Soft Reset: Diabled
74 * [30:30] DRAM CKE pin: Enabled
75 * [29:29] DRAM CLK: Enabled
76 * [28:28] Command Mode: Enabled (For initialization only)
77 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
78 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
79 * [20:19] Read Test: DON'T USE
80 * [18:18] Self Refresh: Enabled
81 * [17:17] 16bit Mode: Disabled
82 * [16:13] Ready Delay: 2
83 * [12:12] Half DQS Delay: Disabled
84 * [11:11] Quarter DQS Delay: Disabled
85 * [10:08] Write Delay: 2
86 * [07:07] Early ODT: Disabled
87 * [06:06] On DIE Termination: Disabled
88 * [05:05] FIFO Overflow Clear: DON'T USE here
89 * [04:04] FIFO Underflow Clear: DON'T USE here
90 * [03:03] FIFO Overflow Pending: DON'T USE here
91 * [02:02] FIFO Underlfow Pending: DON'T USE here
92 * [01:01] FIFO Overlfow Enabled: Enabled
93 * [00:00] FIFO Underflow Enabled: Enabled
94 * TIME_CFG0
95 * [31:16] DRAM Refresh Time: 0 CSB clocks
96 * [15:8] DRAM Command Time: 0 CSB clocks
97 * [07:00] DRAM Precharge Time: 0 CSB clocks
98 * TIME_CFG1
99 * [31:26] DRAM tRFC:
100 * [25:21] DRAM tWR1:
101 * [20:17] DRAM tWRT1:
102 * [16:11] DRAM tDRR:
103 * [10:05] DRAM tRC:
104 * [04:00] DRAM tRAS:
105 * TIME_CFG2
106 * [31:28] DRAM tRCD:
107 * [27:23] DRAM tFAW:
108 * [22:19] DRAM tRTW1:
109 * [18:15] DRAM tCCD:
110 * [14:10] DRAM tRTP:
111 * [09:05] DRAM tRP:
112 * [04:00] DRAM tRPA
113 */
Martha M Stan054197b2009-09-21 14:07:14 -0400114#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
115#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
Stefan Roesee53b5072009-06-09 11:50:40 +0200116#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
117#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
Stefan Roesee53b5072009-06-09 11:50:40 +0200118
Martha M Stan054197b2009-09-21 14:07:14 -0400119#define CONFIG_SYS_DDRCMD_NOP 0x01380000
120#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
121#define CONFIG_SYS_DDRCMD_EM2 0x01020000
122#define CONFIG_SYS_DDRCMD_EM3 0x01030000
123#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
124#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
Stefan Roesee53b5072009-06-09 11:50:40 +0200125#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
Martha M Stan054197b2009-09-21 14:07:14 -0400126#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780
Stefan Roesee53b5072009-06-09 11:50:40 +0200127
128/* DDR Priority Manager Configuration */
129#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
130#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
131#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
132#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
133#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
134#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
135#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
136#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
137#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
138#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
139#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
140#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
141#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
142#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
143#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
144#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
145#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
146#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
147#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
148#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
149#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
150#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
151#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
152
153/*
154 * NOR FLASH on the Local Bus
155 */
156#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
157#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
158
159#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of FLASH */
160#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* max flash size */
161
162#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
163#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
164#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
165#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
166
167#undef CONFIG_SYS_FLASH_CHECKSUM
168
169/*
170 * NAND FLASH
Wolfgang Denk13946922009-06-14 20:58:50 +0200171 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
Stefan Roesee53b5072009-06-09 11:50:40 +0200172 */
173#define CONFIG_CMD_NAND
174#define CONFIG_NAND_MPC5121_NFC
175#define CONFIG_SYS_NAND_BASE 0x40000000
176
177#define CONFIG_SYS_MAX_NAND_DEVICE 1
178#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
179
Wolfgang Denkf5489c42009-06-14 20:58:44 +0200180#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
181
Stefan Roesee53b5072009-06-09 11:50:40 +0200182/*
183 * Configuration parameters for MPC5121 NAND driver
184 */
185#define CONFIG_FSL_NFC_WIDTH 1
186#define CONFIG_FSL_NFC_WRITE_SIZE 2048
187#define CONFIG_FSL_NFC_SPARE_SIZE 64
188#define CONFIG_FSL_NFC_CHIPS 1
189
190#define CONFIG_SYS_SRAM_BASE 0x30000000
191#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
192
193/* ALE active low, data size 4bytes */
194#define CONFIG_SYS_CS0_CFG 0x05051150
195
196/* Use not alternative CS timing */
197#define CONFIG_SYS_CS_ALETIMING 0x00000000
198
199/* ALE active low, data size 4bytes */
200#define CONFIG_SYS_CS1_CFG 0x1f1f3090
201#define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */
202#define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size */
203
204/* Use SRAM for initial stack */
205#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */
206#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
207
208#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
209#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
210#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
211
212#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
213#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Monitor length */
214#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Malloc size */
215
216/*
217 * Serial Port
218 */
219#define CONFIG_CONS_INDEX 1
220#undef CONFIG_SERIAL_SOFTWARE_FIFO
221
222/*
223 * Serial console configuration
224 */
225#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
226#if CONFIG_PSC_CONSOLE != 3
227#error CONFIG_PSC_CONSOLE must be 3
228#endif
229#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
230#define CONFIG_SYS_BAUDRATE_TABLE \
231 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
232
233#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
234#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
235#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
236#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
237
238#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
239/* Use the HUSH parser */
240#define CONFIG_SYS_HUSH_PARSER
241#ifdef CONFIG_SYS_HUSH_PARSER
242#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
243#endif
244
245/* I2C */
246#define CONFIG_HARD_I2C /* I2C with hardware support */
247#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
248#define CONFIG_I2C_MULTI_BUS
Stefan Roesee53b5072009-06-09 11:50:40 +0200249#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
250#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
251
252/*
253 * IIM - IC Identification Module
254 */
255#undef CONFIG_IIM
256
257/*
258 * EEPROM configuration
259 */
260#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
261#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
262#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
263#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
264#define CONFIG_SYS_EEPROM_WREN /* Use EEPROM write protect */
265
266/*
267 * Ethernet configuration
268 */
269#define CONFIG_MPC512x_FEC 1
270#define CONFIG_NET_MULTI
271#define CONFIG_PHY_ADDR 0x1
272#define CONFIG_MII 1 /* MII PHY management */
273#define CONFIG_FEC_AN_TIMEOUT 1
274#define CONFIG_HAS_ETH0
275
276/*
277 * Configure on-board RTC
278 */
279#define CONFIG_SYS_RTC_BUS_NUM 0x01
280#define CONFIG_SYS_I2C_RTC_ADDR 0x32
281#define CONFIG_RTC_RX8025
282
283/*
284 * Environment
285 */
286#define CONFIG_ENV_IS_IN_EEPROM /* Store env in I2C EEPROM */
287#define CONFIG_ENV_SIZE 0x1000
288#define CONFIG_ENV_OFFSET 0x0000 /* environment starts here */
289
290#define CONFIG_LOADS_ECHO /* echo on for serial download */
291#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
292
293#include <config_cmd_default.h>
294
295#define CONFIG_CMD_ASKENV
296#define CONFIG_CMD_DHCP
297#define CONFIG_CMD_I2C
298#define CONFIG_CMD_MII
299#define CONFIG_CMD_NFS
300#define CONFIG_CMD_PING
301#define CONFIG_CMD_REGINFO
302#define CONFIG_CMD_EEPROM
303#define CONFIG_CMD_DATE
304#undef CONFIG_CMD_FUSE
305#undef CONFIG_CMD_IDE
306#undef CONFIG_CMD_EXT2
307#define CONFIG_CMD_FAT
308#define CONFIG_CMD_JFFS2
309#define CONFIG_CMD_ELF
310#define CONFIG_DOS_PARTITION
311
312/*
313 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
314 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
315 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
316 * to chapter 36 of the MPC5121e Reference Manual.
317 */
318/* #define CONFIG_WATCHDOG */ /* enable watchdog */
319#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
320
321 /*
322 * Miscellaneous configurable options
323 */
324#define CONFIG_SYS_LONGHELP /* undef to save memory */
325#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
326#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
327
328#ifdef CONFIG_CMD_KGDB
329# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
330#else
331# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
332#endif
333
334/* Print Buffer Size */
335#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
336 sizeof(CONFIG_SYS_PROMPT) + 16)
337/* max number of command args */
338#define CONFIG_SYS_MAXARGS 32
339/* Boot Argument Buffer Size */
340#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
341
342#define CONFIG_SYS_HZ 1000
343
344/*
345 * For booting Linux, the board info and command line data
346 * have to be in the first 8 MB of memory, since this is
347 * the maximum mapped by the Linux kernel during initialization.
348 */
349#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
350
351/* Cache Configuration */
352#define CONFIG_SYS_DCACHE_SIZE 32768
353#define CONFIG_SYS_CACHELINE_SIZE 32
354#ifdef CONFIG_CMD_KGDB
355#define CONFIG_SYS_CACHELINE_SHIFT 5
356#endif
357
358#define CONFIG_SYS_HID0_INIT 0x000000000
359#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
360#define CONFIG_SYS_HID2 HID2_HBE
361
362#define CONFIG_HIGH_BATS 1 /* High BATs supported */
363
364/*
365 * Internal Definitions
366 *
367 * Boot Flags
368 */
369#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
370#define BOOTFLAG_WARM 0x02 /* Software reboot */
371
372#ifdef CONFIG_CMD_KGDB
373#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
374#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
375#endif
376
377/*
378 * Environment Configuration
379 */
380#define CONFIG_TIMESTAMP
381
382#define CONFIG_HOSTNAME mecp512x
383#define CONFIG_BOOTFILE /tftpboot/mecp512x/uImage
384#define CONFIG_ROOTPATH /tftpboot/mecp512x/target_root
385
386#define CONFIG_LOADADDR 400000 /* def. location for tftp and bootm */
387
388#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
389#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
390
391#define CONFIG_PREBOOT "echo;" \
392 "echo Welcome to MECP5123" \
393 "echo"
394
395#define CONFIG_EXTRA_ENV_SETTINGS \
396 "u-boot_addr_r=200000\0" \
397 "kernel_addr_r=600000\0" \
398 "fdt_addr_r=880000\0" \
399 "ramdisk_addr_r=900000\0" \
400 "u-boot_addr=FFF00000\0" \
401 "kernel_addr=FFC40000\0" \
402 "fdt_addr=FFEC0000\0" \
403 "ramdisk_addr=FC040000\0" \
404 "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0" \
405 "u-boot=/tftpboot/mecp512x/u-boot.bin\0" \
406 "bootfile=/tftpboot/mecp512x/uImage\0" \
407 "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0" \
408 "rootpath=/tftpboot/mecp512x/target_root\n" \
409 "netdev=eth0\0" \
410 "consdev=ttyPSC0\0" \
411 "nfsargs=setenv bootargs root=/dev/nfs rw " \
412 "nfsroot=${serverip}:${rootpath}\0" \
413 "ramargs=setenv bootargs root=/dev/ram rw\0" \
414 "addip=setenv bootargs ${bootargs} " \
415 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
416 ":${hostname}:${netdev}:off panic=1\0" \
417 "addtty=setenv bootargs ${bootargs} " \
418 "console=${consdev},${baudrate}\0" \
419 "flash_nfs=run nfsargs addip addtty;" \
420 "bootm ${kernel_addr} - ${fdt_addr}\0" \
421 "flash_self=run ramargs addip addtty;" \
422 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
423 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
424 "tftp ${fdt_addr_r} ${fdtfile};" \
425 "run nfsargs addip addtty;" \
426 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
427 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
428 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
429 "tftp ${fdt_addr_r} ${fdtfile};" \
430 "run ramargs addip addtty;" \
431 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
432 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
433 "update=protect off ${u-boot_addr} +${filesize};" \
434 "era ${u-boot_addr} +${filesize};" \
435 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
436 "upd=run load update\0" \
437 ""
438
439#define CONFIG_BOOTCOMMAND "run flash_self"
440
441#define CONFIG_OF_LIBFDT
442#define CONFIG_OF_BOARD_SETUP
443
444#define OF_CPU "PowerPC,5121@0"
445#define OF_SOC_COMPAT "fsl,mpc5121-immr"
446#define OF_TBCLK (bd->bi_busfreq / 4)
447#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
448
449#endif /* __CONFIG_H */