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Chander Kashyapa2ac68f2013-08-21 10:38:56 +05301/*
2 * Copyright (C) 2013 Samsung Electronics
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 * Configuration settings for the SAMSUNG Arndale board.
7 */
8
9#ifndef __CONFIG_ARNDALE_H
10#define __CONFIG_ARNDALE_H
11
12/* High Level Configuration Options */
13#define CONFIG_SAMSUNG /* in a SAMSUNG core */
14#define CONFIG_S5P /* S5P Family */
15#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
16#define CONFIG_EXYNOS5250
17
18#include <asm/arch/cpu.h> /* get chip and board defs */
19
20#define CONFIG_SYS_GENERIC_BOARD
21#define CONFIG_ARCH_CPU_INIT
22#define CONFIG_DISPLAY_CPUINFO
23#define CONFIG_DISPLAY_BOARDINFO
24
Chander Kashyapa2ac68f2013-08-21 10:38:56 +053025#define CONFIG_OF_CONTROL
26#define CONFIG_OF_SEPARATE
27
28/* Allow tracing to be enabled */
29#define CONFIG_TRACE
30#define CONFIG_CMD_TRACE
31#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
32#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
33#define CONFIG_TRACE_EARLY
34#define CONFIG_TRACE_EARLY_ADDR 0x50000000
35
36/* Keep L2 Cache Disabled */
37#define CONFIG_SYS_DCACHE_OFF
38
39#define CONFIG_SYS_SDRAM_BASE 0x40000000
40#define CONFIG_SYS_TEXT_BASE 0x43E00000
41
42/* input clock of PLL: SMDK5250 has 24MHz input clock */
43#define CONFIG_SYS_CLK_FREQ 24000000
44
45#define CONFIG_SETUP_MEMORY_TAGS
46#define CONFIG_CMDLINE_TAG
47#define CONFIG_INITRD_TAG
48#define CONFIG_CMDLINE_EDITING
49
50/* Power Down Modes */
51#define S5P_CHECK_SLEEP 0x00000BAD
52#define S5P_CHECK_DIDLE 0xBAD00000
53#define S5P_CHECK_LPA 0xABAD0000
54
55/* Offset for inform registers */
56#define INFORM0_OFFSET 0x800
57#define INFORM1_OFFSET 0x804
58
59/* Size of malloc() pool */
60#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
61
62/* select serial console configuration */
63#define CONFIG_BAUDRATE 115200
64#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
65#define CONFIG_SILENT_CONSOLE
66
67/* Console configuration */
68#define CONFIG_CONSOLE_MUX
69#define CONFIG_SYS_CONSOLE_IS_IN_ENV
70#define EXYNOS_DEVICE_SETTINGS \
71 "stdin=serial\0" \
72 "stdout=serial\0" \
73 "stderr=serial\0"
74
75#define CONFIG_EXTRA_ENV_SETTINGS \
76 EXYNOS_DEVICE_SETTINGS
77
78/* SD/MMC configuration */
79#define CONFIG_GENERIC_MMC
80#define CONFIG_MMC
81#define CONFIG_SDHCI
82#define CONFIG_S5P_SDHCI
83#define CONFIG_DWMMC
84#define CONFIG_EXYNOS_DWMMC
85#define CONFIG_SUPPORT_EMMC_BOOT
Alexey Brodkin2a7a2102013-12-26 15:29:07 +040086#define CONFIG_BOUNCE_BUFFER
Chander Kashyapa2ac68f2013-08-21 10:38:56 +053087
88
89#define CONFIG_BOARD_EARLY_INIT_F
90#define CONFIG_SKIP_LOWLEVEL_INIT
91
92/* PWM */
93#define CONFIG_PWM
94
95/* allow to overwrite serial and ethaddr */
96#define CONFIG_ENV_OVERWRITE
97
98/* Command definition*/
99#include <config_cmd_default.h>
100
101#define CONFIG_CMD_PING
102#define CONFIG_CMD_ELF
103#define CONFIG_CMD_MMC
104#define CONFIG_CMD_EXT2
105#define CONFIG_CMD_FAT
106#define CONFIG_CMD_NET
107#define CONFIG_CMD_HASH
108
109#define CONFIG_BOOTDELAY 3
110#define CONFIG_ZERO_BOOTDELAY_CHECK
111
112/* USB */
113#define CONFIG_CMD_USB
114#define CONFIG_USB_EHCI
115#define CONFIG_USB_EHCI_EXYNOS
116#define CONFIG_USB_STORAGE
117
Inderpal Singh7da76512014-01-08 09:19:57 +0530118#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
119#define CONFIG_USB_HOST_ETHER
120#define CONFIG_USB_ETHER_ASIX
121
Chander Kashyapa2ac68f2013-08-21 10:38:56 +0530122/* MMC SPL */
Rajeshwari Birjee106bd92013-12-26 09:44:24 +0530123#define CONFIG_EXYNOS_SPL
Chander Kashyapa2ac68f2013-08-21 10:38:56 +0530124#define COPY_BL2_FNPTR_ADDR 0x02020030
125
126#define CONFIG_SPL_LIBCOMMON_SUPPORT
127
128/* specific .lds file */
129#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
130#define CONFIG_SPL_TEXT_BASE 0x02023400
131#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
132
133#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
134
135/* Miscellaneous configurable options */
136#define CONFIG_SYS_LONGHELP /* undef to save memory */
137#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
138#define CONFIG_SYS_PROMPT "ARNDALE # "
139#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
140#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
141#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
142#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
143/* Boot Argument Buffer Size */
144#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
145/* memtest works on */
146#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
147#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
148#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
149
Chander Kashyapa2ac68f2013-08-21 10:38:56 +0530150#define CONFIG_RD_LVL
151
152#define CONFIG_NR_DRAM_BANKS 8
153#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
154#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
155#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
156#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
157#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
158#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
159#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
160#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
161#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
162#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
163#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
164#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
165#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
166#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
167#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
168#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
169#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
170
171#define CONFIG_SYS_MONITOR_BASE 0x00000000
172
173/* FLASH and environment organization */
174#define CONFIG_SYS_NO_FLASH
175#undef CONFIG_CMD_IMLS
176#define CONFIG_IDENT_STRING " for ARNDALE"
177
178#define CONFIG_SYS_MMC_ENV_DEV 0
179
180#define CONFIG_ENV_IS_IN_MMC
181#define CONFIG_SECURE_BL1_ONLY
182
183/* Secure FW size configuration */
184#ifdef CONFIG_SECURE_BL1_ONLY
185#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
186#else
187#define CONFIG_SEC_FW_SIZE 0
188#endif
189
190/* Configuration of BL1, BL2, ENV Blocks on mmc */
191#define CONFIG_RES_BLOCK_SIZE (512)
192#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
193#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
194#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
195
196#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
197#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
198#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
199
200/* U-boot copy size from boot Media to DRAM.*/
201#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
202#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
203
Chander Kashyapa2ac68f2013-08-21 10:38:56 +0530204#define CONFIG_DOS_PARTITION
205#define CONFIG_EFI_PARTITION
206#define CONFIG_CMD_PART
207#define CONFIG_PARTITION_UUIDS
208
209
210#define CONFIG_IRAM_STACK 0x02050000
211
212#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
213
214/* I2C */
215#define CONFIG_SYS_I2C_INIT_BOARD
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +0100216#define CONFIG_SYS_I2C
Chander Kashyapa2ac68f2013-08-21 10:38:56 +0530217#define CONFIG_CMD_I2C
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +0100218#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
219#define CONFIG_SYS_I2C_S3C24X0
Chander Kashyapa2ac68f2013-08-21 10:38:56 +0530220#define CONFIG_MAX_I2C_NUM 8
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +0100221#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
Chander Kashyapa2ac68f2013-08-21 10:38:56 +0530222#define CONFIG_I2C_EDID
223
224/* PMIC */
225#define CONFIG_PMIC
Simon Glass913702c2014-05-20 06:01:34 -0600226#define CONFIG_POWER_I2C
227#define CONFIG_POWER_MAX77686
Chander Kashyapa2ac68f2013-08-21 10:38:56 +0530228
229#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale
230
Tushar Beheraf8caed32014-06-10 14:54:18 +0530231#define CONFIG_PREBOOT
232
Chander Kashyapa2ac68f2013-08-21 10:38:56 +0530233/* Ethernet Controllor Driver */
234#ifdef CONFIG_CMD_NET
235#define CONFIG_SMC911X
236#define CONFIG_SMC911X_BASE 0x5000000
237#define CONFIG_SMC911X_16_BIT
238#define CONFIG_ENV_SROM_BANK 1
239#endif /*CONFIG_CMD_NET*/
240
241/* Enable PXE Support */
242#ifdef CONFIG_CMD_NET
243#define CONFIG_CMD_PXE
244#define CONFIG_MENU
245#endif
246
247/* Enable devicetree support */
248#define CONFIG_OF_LIBFDT
249
250/* Enable Time Command */
251#define CONFIG_CMD_TIME
252
Andre Przywarafafbc6c2014-08-01 13:35:44 +0200253#define CONFIG_S5P_PA_SYSRAM 0x02020000
254#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM
255
256/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
257#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
258
259#define CONFIG_ARMV7_VIRT
260
Chander Kashyapa2ac68f2013-08-21 10:38:56 +0530261#endif /* __CONFIG_H */