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Peng Fan9b15ce92019-08-27 06:26:08 +00001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
Peng Fan8d3e37c2020-12-27 14:18:13 +08003 * Copyright 2019-2020 NXP
Peng Fan9b15ce92019-08-27 06:26:08 +00004 */
5
6/dts-v1/;
7
Peng Fan387c4492019-10-16 10:24:30 +00008#include <dt-bindings/usb/pd.h>
Peng Fan8d3e37c2020-12-27 14:18:13 +08009#include "imx8mm-evk.dtsi"
Peng Fan9b15ce92019-08-27 06:26:08 +000010
11/ {
12 model = "FSL i.MX8MM EVK board";
13 compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
14
Peng Fan8d3e37c2020-12-27 14:18:13 +080015 aliases {
16 spi0 = &flexspi;
Peng Fan9b15ce92019-08-27 06:26:08 +000017 };
Peng Fan8d3e37c2020-12-27 14:18:13 +080018};
Peng Fan9b15ce92019-08-27 06:26:08 +000019
Peng Fan8d3e37c2020-12-27 14:18:13 +080020&ddrc {
21 operating-points-v2 = <&ddrc_opp_table>;
Peng Fan9b15ce92019-08-27 06:26:08 +000022
Peng Fan8d3e37c2020-12-27 14:18:13 +080023 ddrc_opp_table: opp-table {
24 compatible = "operating-points-v2";
Peng Fan9b15ce92019-08-27 06:26:08 +000025
Peng Fan8d3e37c2020-12-27 14:18:13 +080026 opp-25M {
27 opp-hz = /bits/ 64 <25000000>;
Peng Fan387c4492019-10-16 10:24:30 +000028 };
29
Peng Fan8d3e37c2020-12-27 14:18:13 +080030 opp-100M {
31 opp-hz = /bits/ 64 <100000000>;
32 };
33
34 opp-750M {
35 opp-hz = /bits/ 64 <750000000>;
Peng Fan387c4492019-10-16 10:24:30 +000036 };
37 };
38};
39
Peng Fan8d3e37c2020-12-27 14:18:13 +080040&flexspi {
Peng Fan9b15ce92019-08-27 06:26:08 +000041 pinctrl-names = "default";
Peng Fan8d3e37c2020-12-27 14:18:13 +080042 pinctrl-0 = <&pinctrl_flexspi>;
Peng Fan9b15ce92019-08-27 06:26:08 +000043 status = "okay";
44
Peng Fan8d3e37c2020-12-27 14:18:13 +080045 flash@0 {
46 reg = <0>;
Peng Fan9b15ce92019-08-27 06:26:08 +000047 #address-cells = <1>;
Peng Fan8d3e37c2020-12-27 14:18:13 +080048 #size-cells = <1>;
49 compatible = "jedec,spi-nor";
50 spi-max-frequency = <80000000>;
Marcel Ziswiler24a7a3c2022-07-21 15:27:40 +020051 spi-tx-bus-width = <1>;
Peng Fan8d3e37c2020-12-27 14:18:13 +080052 spi-rx-bus-width = <4>;
Peng Fan9b15ce92019-08-27 06:26:08 +000053 };
54};
55
Peng Fan9b15ce92019-08-27 06:26:08 +000056&usdhc3 {
Peng Fan8d3e37c2020-12-27 14:18:13 +080057 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
58 assigned-clock-rates = <400000000>;
Peng Fan9b15ce92019-08-27 06:26:08 +000059 pinctrl-names = "default", "state_100mhz", "state_200mhz";
60 pinctrl-0 = <&pinctrl_usdhc3>;
61 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
62 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
63 bus-width = <8>;
64 non-removable;
65 status = "okay";
66};
67
Peng Fan9b15ce92019-08-27 06:26:08 +000068&iomuxc {
Peng Fan8d3e37c2020-12-27 14:18:13 +080069 pinctrl_flexspi: flexspigrp {
Peng Fan9b15ce92019-08-27 06:26:08 +000070 fsl,pins = <
Peng Fan8d3e37c2020-12-27 14:18:13 +080071 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
72 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
73 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
74 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
75 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
76 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
Peng Fan9b15ce92019-08-27 06:26:08 +000077 >;
78 };
79
80 pinctrl_usdhc3: usdhc3grp {
81 fsl,pins = <
Peng Fan8d3e37c2020-12-27 14:18:13 +080082 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
83 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
84 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
85 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
86 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
87 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
88 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
89 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
90 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
91 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
92 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
93 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
Peng Fan9b15ce92019-08-27 06:26:08 +000094 >;
95 };
96
Peng Fan8d3e37c2020-12-27 14:18:13 +080097 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
Peng Fan9b15ce92019-08-27 06:26:08 +000098 fsl,pins = <
Peng Fan8d3e37c2020-12-27 14:18:13 +080099 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
100 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
101 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
102 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
103 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
104 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
105 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
106 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
107 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
108 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
109 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
Peng Fan9b15ce92019-08-27 06:26:08 +0000110 >;
111 };
112
Peng Fan8d3e37c2020-12-27 14:18:13 +0800113 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
Peng Fan9b15ce92019-08-27 06:26:08 +0000114 fsl,pins = <
Peng Fan8d3e37c2020-12-27 14:18:13 +0800115 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
116 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
117 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
118 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
119 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
120 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
121 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
122 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
123 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
124 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
125 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
Peng Fan9b15ce92019-08-27 06:26:08 +0000126 >;
127 };
128};