blob: c15c7fea47fedc114a4f5919921d6e57446affd5 [file] [log] [blame]
Neil Armstrong59beb232018-04-23 16:19:23 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
4 * Copyright (C) 2018 BayLibre, SAS
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
8 */
9
10#include <common.h>
11#include <adc.h>
12#include <clk.h>
13#include <dm.h>
14#include <regmap.h>
15#include <errno.h>
16#include <asm/io.h>
Simon Glasscd93d622020-05-10 11:40:13 -060017#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060018#include <linux/delay.h>
Neil Armstrong59beb232018-04-23 16:19:23 +020019#include <linux/math64.h>
20#include <linux/bitfield.h>
Simon Glass1e94b462023-09-14 18:21:46 -060021#include <linux/printk.h>
Marek Szyprowski97ab8022021-02-18 11:33:16 +010022#include <power/regulator.h>
Neil Armstrong59beb232018-04-23 16:19:23 +020023
24#define MESON_SAR_ADC_REG0 0x00
25 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
26 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
27 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
28 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
29 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
30 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
31 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
32 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
33 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
34 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
35 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
36 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
37 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
38 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
39 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
40 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
41 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
42 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
43 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
44 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
45
46#define MESON_SAR_ADC_CHAN_LIST 0x04
47 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
48 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
49 (GENMASK(2, 0) << ((_chan) * 3))
50
51#define MESON_SAR_ADC_AVG_CNTL 0x08
52 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
53 (16 + ((_chan) * 2))
54 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
55 (GENMASK(17, 16) << ((_chan) * 2))
56 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
57 (0 + ((_chan) * 2))
58 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
59 (GENMASK(1, 0) << ((_chan) * 2))
60
61#define MESON_SAR_ADC_REG3 0x0c
62 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
63 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
64 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
65 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
66 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
67 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
68 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
69 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
70 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
71 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
72 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
73 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
74 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
75 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
76
77#define MESON_SAR_ADC_DELAY 0x10
78 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
79 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
80 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
81 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
82 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
83 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
84
85#define MESON_SAR_ADC_LAST_RD 0x14
86 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
87 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
88
89#define MESON_SAR_ADC_FIFO_RD 0x18
90 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
91 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
92
93#define MESON_SAR_ADC_AUX_SW 0x1c
94 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
95 (8 + (((_chan) - 2) * 3))
96 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
97 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
98 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
99 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
100 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
101 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
102 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
103
104#define MESON_SAR_ADC_CHAN_10_SW 0x20
105 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
106 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
107 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
121
122#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
123 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
124 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
125 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
132 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
133 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
134 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
136 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
140
141#define MESON_SAR_ADC_DELTA_10 0x28
142 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
143 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
144 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
145 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
146 #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
147 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
148 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
149 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
150
151/*
152 * NOTE: registers from here are undocumented (the vendor Linux kernel driver
153 * and u-boot source served as reference). These only seem to be relevant on
154 * GXBB and newer.
155 */
156#define MESON_SAR_ADC_REG11 0x2c
157 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
158
159#define MESON_SAR_ADC_REG13 0x34
160 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
161
162#define MESON_SAR_ADC_MAX_FIFO_SIZE 32
163#define MESON_SAR_ADC_TIMEOUT 100 /* ms */
164
165#define NUM_CHANNELS 8
166
167#define MILLION 1000000
168
169struct meson_saradc_data {
170 int num_bits;
171};
172
173struct meson_saradc_priv {
174 const struct meson_saradc_data *data;
175 struct regmap *regmap;
176 struct clk core_clk;
177 struct clk adc_clk;
178 bool initialized;
179 int active_channel;
180 int calibbias;
181 int calibscale;
182};
183
184static unsigned int
185meson_saradc_get_fifo_count(struct meson_saradc_priv *priv)
186{
187 u32 regval;
188
189 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
190
191 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
192}
193
194static int meson_saradc_lock(struct meson_saradc_priv *priv)
195{
196 uint val, timeout = 10000;
197
198 /* prevent BL30 from using the SAR ADC while we are using it */
199 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
200 MESON_SAR_ADC_DELAY_KERNEL_BUSY,
201 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
202
203 /*
204 * wait until BL30 releases it's lock (so we can use the SAR ADC)
205 */
206 do {
207 udelay(1);
208 regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
209 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
210
211 if (timeout < 0) {
212 printf("Timeout while waiting for BL30 unlock\n");
213 return -ETIMEDOUT;
214 }
215
216 return 0;
217}
218
219static void meson_saradc_unlock(struct meson_saradc_priv *priv)
220{
221 /* allow BL30 to use the SAR ADC again */
222 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
223 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
224}
225
226static void meson_saradc_clear_fifo(struct meson_saradc_priv *priv)
227{
228 unsigned int count, tmp;
229
230 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
231 if (!meson_saradc_get_fifo_count(priv))
232 break;
233
234 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
235 }
236}
237
238static int meson_saradc_calib_val(struct meson_saradc_priv *priv, int val)
239{
240 int tmp;
241
242 /* use val_calib = scale * val_raw + offset calibration function */
243 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
244
245 return clamp(tmp, 0, (1 << priv->data->num_bits) - 1);
246}
247
248static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv)
249{
250 uint regval, timeout = 10000;
251
252 /*
253 * NOTE: we need a small delay before reading the status, otherwise
254 * the sample engine may not have started internally (which would
255 * seem to us that sampling is already finished).
256 */
257 do {
258 udelay(1);
259 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
260 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
261
262 if (timeout < 0)
263 return -ETIMEDOUT;
264
265 return 0;
266}
267
268static int meson_saradc_read_raw_sample(struct meson_saradc_priv *priv,
269 unsigned int channel, uint *val)
270{
271 uint regval, fifo_chan, fifo_val, count;
272 int ret;
273
274 ret = meson_saradc_wait_busy_clear(priv);
275 if (ret)
276 return ret;
277
278 count = meson_saradc_get_fifo_count(priv);
279 if (count != 1) {
280 printf("ADC FIFO has %d element(s) instead of one\n", count);
281 return -EINVAL;
282 }
283
284 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
285 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
286 if (fifo_chan != channel) {
Heinrich Schuchardtd50b7362020-12-27 09:46:46 +0100287 printf("ADC FIFO entry belongs to channel %u instead of %u\n",
Neil Armstrong59beb232018-04-23 16:19:23 +0200288 fifo_chan, channel);
289 return -EINVAL;
290 }
291
292 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
293 fifo_val &= GENMASK(priv->data->num_bits - 1, 0);
294 *val = meson_saradc_calib_val(priv, fifo_val);
295
296 return 0;
297}
298
299static void meson_saradc_start_sample_engine(struct meson_saradc_priv *priv)
300{
301 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
302 MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
303 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
304
305 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
306 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
307 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
308
309 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
310 MESON_SAR_ADC_REG0_SAMPLING_START,
311 MESON_SAR_ADC_REG0_SAMPLING_START);
312}
313
314static void meson_saradc_stop_sample_engine(struct meson_saradc_priv *priv)
315{
316 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
317 MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
318
319 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
320 MESON_SAR_ADC_REG0_SAMPLING_STOP,
321 MESON_SAR_ADC_REG0_SAMPLING_STOP);
322
323 /* wait until all modules are stopped */
324 meson_saradc_wait_busy_clear(priv);
325
326 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
327 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
328}
329
330enum meson_saradc_avg_mode {
331 NO_AVERAGING = 0x0,
332 MEAN_AVERAGING = 0x1,
333 MEDIAN_AVERAGING = 0x2,
334};
335
336enum meson_saradc_num_samples {
337 ONE_SAMPLE = 0x0,
338 TWO_SAMPLES = 0x1,
339 FOUR_SAMPLES = 0x2,
340 EIGHT_SAMPLES = 0x3,
341};
342
343static void meson_saradc_set_averaging(struct meson_saradc_priv *priv,
344 unsigned int channel,
345 enum meson_saradc_avg_mode mode,
346 enum meson_saradc_num_samples samples)
347{
348 int val;
349
350 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
351 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
352 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
353 val);
354
355 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
356 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
357 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
358}
359
360static void meson_saradc_enable_channel(struct meson_saradc_priv *priv,
361 unsigned int channel)
362{
363 uint regval;
364
365 /*
366 * the SAR ADC engine allows sampling multiple channels at the same
367 * time. to keep it simple we're only working with one *internal*
368 * channel, which starts counting at index 0 (which means: count = 1).
369 */
370 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
371 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
372 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
373
374 /* map channel index 0 to the channel which we want to read */
375 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), channel);
376 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
377 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
378
379 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
380 channel);
381 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
382 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
383 regval);
384
385 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
386 channel);
387 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
388 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
389 regval);
390
391 if (channel == 6)
392 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
393 MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
394}
395
396static int meson_saradc_get_sample(struct meson_saradc_priv *priv,
397 int chan, uint *val)
398{
399 int ret;
400
401 ret = meson_saradc_lock(priv);
402 if (ret)
403 return ret;
404
405 /* clear the FIFO to make sure we're not reading old values */
406 meson_saradc_clear_fifo(priv);
407
408 meson_saradc_set_averaging(priv, chan, MEAN_AVERAGING, EIGHT_SAMPLES);
409
410 meson_saradc_enable_channel(priv, chan);
411
412 meson_saradc_start_sample_engine(priv);
413 ret = meson_saradc_read_raw_sample(priv, chan, val);
414 meson_saradc_stop_sample_engine(priv);
415
416 meson_saradc_unlock(priv);
417
418 if (ret) {
419 printf("failed to read sample for channel %d: %d\n",
420 chan, ret);
421 return ret;
422 }
423
424 return 0;
425}
426
427static int meson_saradc_channel_data(struct udevice *dev, int channel,
428 unsigned int *data)
429{
430 struct meson_saradc_priv *priv = dev_get_priv(dev);
431
432 if (channel != priv->active_channel) {
433 pr_err("Requested channel is not active!");
434 return -EINVAL;
435 }
436
437 return meson_saradc_get_sample(priv, channel, data);
438}
439
440enum meson_saradc_chan7_mux_sel {
441 CHAN7_MUX_VSS = 0x0,
442 CHAN7_MUX_VDD_DIV4 = 0x1,
443 CHAN7_MUX_VDD_DIV2 = 0x2,
444 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
445 CHAN7_MUX_VDD = 0x4,
446 CHAN7_MUX_CH7_INPUT = 0x7,
447};
448
449static void meson_saradc_set_chan7_mux(struct meson_saradc_priv *priv,
450 enum meson_saradc_chan7_mux_sel sel)
451{
452 u32 regval;
453
454 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
455 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
456 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
457
458 udelay(20);
459}
460
461static int meson_saradc_calib(struct meson_saradc_priv *priv)
462{
463 uint nominal0, nominal1, value0, value1;
464 int ret;
465
466 /* use points 25% and 75% for calibration */
467 nominal0 = (1 << priv->data->num_bits) / 4;
468 nominal1 = (1 << priv->data->num_bits) * 3 / 4;
469
470 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_DIV4);
471 udelay(20);
472 ret = meson_saradc_get_sample(priv, 7, &value0);
473 if (ret < 0)
474 goto out;
475
476 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_MUL3_DIV4);
477 udelay(20);
478 ret = meson_saradc_get_sample(priv, 7, &value1);
479 if (ret < 0)
480 goto out;
481
482 if (value1 <= value0) {
483 ret = -EINVAL;
484 goto out;
485 }
486
487 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
488 value1 - value0);
489 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
490 MILLION);
491 ret = 0;
492out:
493 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
494
495 return ret;
496}
497
498static int meson_saradc_init(struct meson_saradc_priv *priv)
499{
500 uint regval;
501 int ret, i;
502
503 priv->calibscale = MILLION;
504
505 /*
506 * make sure we start at CH7 input since the other muxes are only used
507 * for internal calibration.
508 */
509 meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
510
511 /*
512 * leave sampling delay and the input clocks as configured by
513 * BL30 to make sure BL30 gets the values it expects when
514 * reading the temperature sensor.
515 */
516 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
Marek Szyprowski81b1c472020-12-16 08:51:55 +0100517 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) {
518 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
519 if (regval & MESON_SAR_ADC_REG3_ADC_EN)
520 return 0;
521 }
Neil Armstrong59beb232018-04-23 16:19:23 +0200522
523 meson_saradc_stop_sample_engine(priv);
524
525 /* update the channel 6 MUX to select the temperature sensor */
526 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
527 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
528 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
529
530 /* disable all channels by default */
531 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
532
533 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
534 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
535 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
536 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
537 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
538
539 /* delay between two samples = (10+1) * 1uS */
540 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
541 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
542 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
543 10));
544 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
545 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
546 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
547 0));
548
549 /* delay between two samples = (10+1) * 1uS */
550 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
551 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
552 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
553 10));
554 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
555 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
556 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
557 1));
558
559 /*
560 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
561 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
562 */
563 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
564 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
565 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
566 regval);
567 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
568 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
569 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
570 regval);
571
572 /*
573 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
574 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
575 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
576 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
577 */
578 regval = 0;
579 for (i = 2; i <= 7; i++)
580 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
581 regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
582 regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
583 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
584
585 ret = meson_saradc_lock(priv);
586 if (ret)
587 return ret;
588
589#if CONFIG_IS_ENABLED(CLK)
590 ret = clk_enable(&priv->core_clk);
591 if (ret)
592 return ret;
593#endif
594
595 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
596 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
597 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
598
599 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
600 MESON_SAR_ADC_REG11_BANDGAP_EN,
601 MESON_SAR_ADC_REG11_BANDGAP_EN);
602
603 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
604 MESON_SAR_ADC_REG3_ADC_EN,
605 MESON_SAR_ADC_REG3_ADC_EN);
606
607 udelay(5);
608
609#if CONFIG_IS_ENABLED(CLK)
610 ret = clk_enable(&priv->adc_clk);
611 if (ret)
612 return ret;
613#endif
614
615 meson_saradc_unlock(priv);
616
617 ret = meson_saradc_calib(priv);
618 if (ret) {
619 printf("calibration failed\n");
620 return -EIO;
621 }
622
623 return 0;
624}
625
626static int meson_saradc_start_channel(struct udevice *dev, int channel)
627{
628 struct meson_saradc_priv *priv = dev_get_priv(dev);
629
630 if (channel < 0 || channel >= NUM_CHANNELS) {
631 printf("Requested channel is invalid!");
632 return -EINVAL;
633 }
634
635 if (!priv->initialized) {
636 int ret;
637
638 ret = meson_saradc_init(priv);
639 if (ret)
640 return ret;
641
642 priv->initialized = true;
643 }
644
645 priv->active_channel = channel;
646
647 return 0;
648}
649
650static int meson_saradc_stop(struct udevice *dev)
651{
652 struct meson_saradc_priv *priv = dev_get_priv(dev);
653
654 priv->active_channel = -1;
655
656 return 0;
657}
658
659static int meson_saradc_probe(struct udevice *dev)
660{
Marek Szyprowski97ab8022021-02-18 11:33:16 +0100661 struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
Neil Armstrong59beb232018-04-23 16:19:23 +0200662 struct meson_saradc_priv *priv = dev_get_priv(dev);
Marek Szyprowski97ab8022021-02-18 11:33:16 +0100663 struct udevice *vref;
664 int vref_uv;
Neil Armstrong59beb232018-04-23 16:19:23 +0200665 int ret;
666
Neil Armstrong0421c982018-06-14 13:43:37 +0200667 ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
Neil Armstrong59beb232018-04-23 16:19:23 +0200668 if (ret)
669 return ret;
670
671#if CONFIG_IS_ENABLED(CLK)
672 ret = clk_get_by_name(dev, "core", &priv->core_clk);
673 if (ret)
674 return ret;
675
676 ret = clk_get_by_name(dev, "adc_clk", &priv->adc_clk);
677 if (ret)
678 return ret;
679#endif
680
681 priv->active_channel = -1;
682
Marek Szyprowski97ab8022021-02-18 11:33:16 +0100683 ret = device_get_supply_regulator(dev, "vref-supply", &vref);
684 if (ret) {
685 printf("can't get vref-supply: %d\n", ret);
686 return ret;
687 }
688
689 vref_uv = regulator_get_value(vref);
690 if (vref_uv < 0) {
691 printf("can't get vref-supply value: %d\n", vref_uv);
692 return vref_uv;
693 }
694
695 /* VDD supplied by common vref pin */
696 uc_pdata->vdd_supply = vref;
697 uc_pdata->vdd_microvolts = vref_uv;
698 uc_pdata->vss_microvolts = 0;
699
Neil Armstrong59beb232018-04-23 16:19:23 +0200700 return 0;
701}
702
Simon Glassd1998a92020-12-03 16:55:21 -0700703int meson_saradc_of_to_plat(struct udevice *dev)
Neil Armstrong59beb232018-04-23 16:19:23 +0200704{
Simon Glasscaa4daa2020-12-03 16:55:18 -0700705 struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
Neil Armstrong59beb232018-04-23 16:19:23 +0200706 struct meson_saradc_priv *priv = dev_get_priv(dev);
707
708 priv->data = (struct meson_saradc_data *)dev_get_driver_data(dev);
709
710 uc_pdata->data_mask = GENMASK(priv->data->num_bits - 1, 0);
711 uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
712 uc_pdata->data_timeout_us = MESON_SAR_ADC_TIMEOUT * 1000;
713 uc_pdata->channel_mask = GENMASK(NUM_CHANNELS - 1, 0);
714
715 return 0;
716}
717
718static const struct adc_ops meson_saradc_ops = {
719 .start_channel = meson_saradc_start_channel,
720 .channel_data = meson_saradc_channel_data,
721 .stop = meson_saradc_stop,
722};
723
724static const struct meson_saradc_data gxbb_saradc_data = {
725 .num_bits = 10,
726};
727
728static const struct meson_saradc_data gxl_saradc_data = {
729 .num_bits = 12,
730};
731
732static const struct udevice_id meson_saradc_ids[] = {
733 { .compatible = "amlogic,meson-gxbb-saradc",
734 .data = (ulong)&gxbb_saradc_data },
735 { .compatible = "amlogic,meson-gxl-saradc",
736 .data = (ulong)&gxl_saradc_data },
737 { .compatible = "amlogic,meson-gxm-saradc",
738 .data = (ulong)&gxl_saradc_data },
Marek Szyprowski220992b2020-12-16 08:51:54 +0100739 { .compatible = "amlogic,meson-g12a-saradc",
740 .data = (ulong)&gxl_saradc_data },
Vyacheslav Bocharov8a4a73f2022-04-24 11:21:57 +0300741 { .compatible = "amlogic,meson-axg-saradc",
742 .data = (ulong)&gxl_saradc_data },
Neil Armstrong59beb232018-04-23 16:19:23 +0200743 { }
744};
745
746U_BOOT_DRIVER(meson_saradc) = {
747 .name = "meson_saradc",
748 .id = UCLASS_ADC,
749 .of_match = meson_saradc_ids,
750 .ops = &meson_saradc_ops,
751 .probe = meson_saradc_probe,
Simon Glassd1998a92020-12-03 16:55:21 -0700752 .of_to_plat = meson_saradc_of_to_plat,
Simon Glass41575d82020-12-03 16:55:17 -0700753 .priv_auto = sizeof(struct meson_saradc_priv),
Neil Armstrong59beb232018-04-23 16:19:23 +0200754};