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wdenk1d589e32001-01-20 01:23:52 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk1d589e32001-01-20 01:23:52 +00006 */
7
8/*
9 * defines for Cogent Motherboards
10 */
11
12#ifndef _COGENT_MB_H
13#define _COGENT_MB_H
14
15/*
16 * Cogent Motherboard Address Map
17 *
18 * The size of a Cogent motherboard address space is 256 Mbytes (i.e. 28 bits).
19 *
20 * The first 32 Mbyte (0x0000000-0x1FFFFFF) is usually RAM. The following
21 * 3 x 32 Mbyte areas (0x2000000-0x3FFFFFF, 0x4000000-0x5FFFFFF and
22 * 0x6000000-0x7FFFFFF) are general I/O "slots" (slots 1, 2 and 3).
23 * Most other motherboard devices have registers mapped into the area
24 * 0xE000000-0xFFFFFFF (Motherboard I/O slot?). The area 0x8000000-0xDFFFFFF
25 * is free for whatever.
26 *
27 * The location of the motherboard address space in the physical address space
28 * of the cpu is given by CMA_MB_BASE. This value is determined by the cpu
29 * module plugged into the motherboard and is configured above.
30 *
31 * Motherboard I/O devices mapped into the area (0xE000000-0xFFFFFFF)
32 * generally only use byte lane 0 (D0-7) for their transfers, i.e. only
33 * 8 bit, or 1 byte, transfers can take place, so all the registers are
34 * only 8 bits wide. The exceptions are the motherboard flash, which uses
35 * byte lanes 0 and 1 (i.e. 16 bits), and the mapped PCI address space.
36 *
37 * I/O registers within the mapped motherboard devices are 64 bit aligned
38 * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register
39 * will be at byte 7 (the address + 7). For little endian addressing, the
40 * register will be at byte 0 (the address + 0). To learn the endianess
wdenkda93ed82004-09-29 11:02:56 +000041 * we must include <endian.h>
wdenk1d589e32001-01-20 01:23:52 +000042 *
43 * Take the CMA102 and CMA111 motherboards as examples...
44 *
45 * The CMA102 has three CMABus I/O Expansion slots and no PCI bridge. The 3
46 * CMABus slots are each mapped directly onto the three general I/O slots.
47 *
48 * The CMA111 has only one CMABus I/O Expansion slot, but has a V360EPC PCI
49 * bridge. The CMABus slot is mapped onto general I/O slot 1. The standard
50 * PCI Bus space is mapped onto general I/O slot 2, with a small area at the
51 * top reserved for access to the V360EPC registers (0x5FF0000-0x5FFFFFF).
52 * I/O slot 3 is unused. The extended PCI Bus space is mapped onto the area
53 * 0xA000000-0xDFFFFFF.
54 */
55
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CMA_MB_RAM_BASE (CONFIG_SYS_CMA_MB_BASE+0x0000000)
wdenk1d589e32001-01-20 01:23:52 +000057#define CMA_MB_RAM_SIZE 0x2000000 /* dip sws set actual size */
58
59#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CMA_MB_SLOT1_BASE (CONFIG_SYS_CMA_MB_BASE+0x2000000)
wdenk1d589e32001-01-20 01:23:52 +000061#define CMA_MB_SLOT1_SIZE 0x2000000
62#endif
63
64#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CMA_MB_SLOT2_BASE (CONFIG_SYS_CMA_MB_BASE+0x4000000)
wdenk1d589e32001-01-20 01:23:52 +000066#define CMA_MB_SLOT2_SIZE 0x2000000
67#endif
68#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CMA_MB_STDPCI_BASE (CONFIG_SYS_CMA_MB_BASE+0x4000000)
wdenk1d589e32001-01-20 01:23:52 +000070#define CMA_MB_STDPCI_SIZE 0x1ff0000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CMA_MB_V360EPC_BASE (CONFIG_SYS_CMA_MB_BASE+0x5ff0000)
wdenk1d589e32001-01-20 01:23:52 +000072#define CMA_MB_V360EPC_SIZE 0x10000
73#endif
74
75#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CMA_MB_SLOT3_BASE (CONFIG_SYS_CMA_MB_BASE+0x6000000)
wdenk1d589e32001-01-20 01:23:52 +000077#define CMA_MB_SLOT3_SIZE 0x2000000
78#endif
79
80#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CMA_MB_EXTPCI_BASE (CONFIG_SYS_CMA_MB_BASE+0xa000000)
wdenk1d589e32001-01-20 01:23:52 +000082#define CMA_MB_EXTPCI_SIZE 0x4000000
83#endif
84
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CMA_MB_ROMLOW_BASE (CONFIG_SYS_CMA_MB_BASE+0xe000000)
wdenk1d589e32001-01-20 01:23:52 +000086#define CMA_MB_ROMLOW_SIZE 0x800000
87#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CMA_MB_FLLOW_EXEC_BASE (CONFIG_SYS_CMA_MB_BASE+0xe000000)
wdenk1d589e32001-01-20 01:23:52 +000089#define CMA_MB_FLLOW_EXEC_SIZE 0x100000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CMA_MB_FLLOW_RDWR_BASE (CONFIG_SYS_CMA_MB_BASE+0xe400000)
wdenk1d589e32001-01-20 01:23:52 +000091#define CMA_MB_FLLOW_RDWR_SIZE 0x400000
92#endif
93
94#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CMA_MB_RTC_BASE (CONFIG_SYS_CMA_MB_BASE+0xe800000)
wdenk1d589e32001-01-20 01:23:52 +000096#define CMA_MB_RTC_SIZE 0x4000
97#endif
98
99#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CMA_MB_SERPAR_BASE (CONFIG_SYS_CMA_MB_BASE+0xe900000)
wdenk1d589e32001-01-20 01:23:52 +0000101#define CMA_MB_SERIALB_BASE (CMA_MB_SERPAR_BASE+0x00)
102#define CMA_MB_SERIALA_BASE (CMA_MB_SERPAR_BASE+0x40)
103#define CMA_MB_PARALLEL_BASE (CMA_MB_SERPAR_BASE+0x80)
104#define CMA_MB_SERPAR_SIZE 0xa0
105#endif
106
107#if (CMA_MB_CAPS & CMA_MB_CAP_KBM)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CMA_MB_PKBM_BASE (CONFIG_SYS_CMA_MB_BASE+0xe900100)
wdenk1d589e32001-01-20 01:23:52 +0000109#define CMA_MB_PKBM_SIZE 0x10
110#endif
111
112#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CMA_MB_LCD_BASE (CONFIG_SYS_CMA_MB_BASE+0xeb00000)
wdenk1d589e32001-01-20 01:23:52 +0000114#define CMA_MB_LCD_SIZE 0x10
115#endif
116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CMA_MB_DIPSW_BASE (CONFIG_SYS_CMA_MB_BASE+0xec00000)
wdenk1d589e32001-01-20 01:23:52 +0000118#define CMA_MB_DIPSW_SIZE 0x10
119
120#if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CMA_MB_SLOT1CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf100000)
wdenk1d589e32001-01-20 01:23:52 +0000122#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
123#define CMA_MB_SER2_BASE (CMA_MB_SLOT1CFG_BASE+0x80)
124#define CMA_MB_SER2B_BASE (CMA_MB_SER2_BASE+0x00)
125#define CMA_MB_SER2A_BASE (CMA_MB_SER2_BASE+0x40)
126#endif
127#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT1)
128#define CMA_MB_S1KBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200)
129#endif
130#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) && !defined(COGENT_CMA150)
131#define CMA_MB_IREQ1STAT_BASE (CMA_MB_SLOT1CFG_BASE+0x100)
132#define CMA_MB_AKBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200)
133#define CMA_MB_IREQ1MASK_BASE (CMA_MB_SLOT1CFG_BASE+0x300)
134#endif
135#define CMA_MB_SLOT1CFG_SIZE 0x400
136#endif
137
138#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CMA_MB_SLOT2CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf200000)
wdenk1d589e32001-01-20 01:23:52 +0000140#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2)
141#define CMA_MB_S2KBM_BASE (CMA_MB_SLOT2CFG_BASE+0x200)
142#endif
143#define CMA_MB_SLOT2CFG_SIZE 0x400
144#endif
145
146#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CMA_MB_PCICTL_BASE (CONFIG_SYS_CMA_MB_BASE+0xf200000)
wdenk1d589e32001-01-20 01:23:52 +0000148#define CMA_MB_PCI_V3CTL_BASE (CMA_MB_PCICTL_BASE+0x100)
149#define CMA_MB_PCI_IDSEL_BASE (CMA_MB_PCICTL_BASE+0x200)
150#define CMA_MB_PCI_IMASK_BASE (CMA_MB_PCICTL_BASE+0x300)
151#define CMA_MB_PCI_ISTAT_BASE (CMA_MB_PCICTL_BASE+0x400)
152#define CMA_MB_PCI_MBID_BASE (CMA_MB_PCICTL_BASE+0x500)
153#define CMA_MB_PCI_MBREV_BASE (CMA_MB_PCICTL_BASE+0x600)
154#define CMA_MB_PCICTL_SIZE 0x700
155#endif
156
157#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CMA_MB_SLOT3CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf300000)
wdenk1d589e32001-01-20 01:23:52 +0000159#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3)
160#define CMA_MB_S3KBM_BASE (CMA_MB_SLOT3CFG_BASE+0x200)
161#endif
162#define CMA_MB_SLOT3CFG_SIZE 0x400
163#endif
164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CMA_MB_ROMHIGH_BASE (CONFIG_SYS_CMA_MB_BASE+0xf800000)
wdenk1d589e32001-01-20 01:23:52 +0000166#define CMA_MB_ROMHIGH_SIZE 0x800000
167#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CMA_MB_FLHIGH_EXEC_BASE (CONFIG_SYS_CMA_MB_BASE+0xf800000)
wdenk1d589e32001-01-20 01:23:52 +0000169#define CMA_MB_FLHIGH_EXEC_SIZE 0x100000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CMA_MB_FLHIGH_RDWR_BASE (CONFIG_SYS_CMA_MB_BASE+0xfc00000)
wdenk1d589e32001-01-20 01:23:52 +0000171#define CMA_MB_FLHIGH_RDWR_SIZE 0x400000
172#endif
173
174#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
175
176/* PCI Control Register bits */
177
178/* V360EPC Control register bits */
179#define CMA_MB_PCI_V3CTL_RESET 0x01
180#define CMA_MB_PCI_V3CTL_EXTADD 0x08
181
182/* PCI ID Select register bits */
183#define CMA_MB_PCI_IDSEL_SLOTA 0x01
184#define CMA_MB_PCI_IDSEL_SLOTB 0x02
185#define CMA_MB_PCI_IDSEL_GD82559 0x04
186#define CMA_MB_PCI_IDSEL_B69000 0x08
187#define CMA_MB_PCI_IDSEL_PD6832 0x10
188
189/* PCI Interrupt Mask/Status register bits */
190#define CMA_MB_PCI_IMS_INTA 0x01
191#define CMA_MB_PCI_IMS_INTB 0x02
192#define CMA_MB_PCI_IMS_INTC 0x04
193#define CMA_MB_PCI_IMS_INTD 0x08
194#define CMA_MB_PCI_IMS_CBINT 0x10
195#define CMA_MB_PCI_IMS_V3LINT 0x80
196
197#endif
198
199#if (CMA_MB_CAPS & (CMA_MB_CAP_KBM|CMA_MB_CAP_SER2)) && !defined(COGENT_CMA150)
200
201/*
202 * IREQ1 Interrupt Mask/Status register bits
203 * (Note: not available on CMA150 - must poll HT6542B interrupt register)
204 */
205
206#define IREQ1_MINT 0x01
207#define IREQ1_KINT 0x02
208#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
209#define IREQ1_SINT2 0x04
210#define IREQ1_SINT3 0x08
211#endif
212
213#endif
214
215#ifndef __ASSEMBLY__
216
wdenkda93ed82004-09-29 11:02:56 +0000217#ifdef USE_HOSTCC
218#include <endian.h> /* avoid using private kernel header files */
219#else
220#include <asm/byteorder.h> /* use U-Boot provided headers */
221#endif
wdenk1d589e32001-01-20 01:23:52 +0000222
223/* a single CMA10x motherboard i/o register */
224typedef
225 struct {
wdenkda93ed82004-09-29 11:02:56 +0000226#if __BYTE_ORDER == __LITTLE_ENDIAN
wdenk1d589e32001-01-20 01:23:52 +0000227 unsigned char value;
228#endif
229 unsigned char filler[7];
wdenkda93ed82004-09-29 11:02:56 +0000230#if __BYTE_ORDER == __BIG_ENDIAN
wdenk1d589e32001-01-20 01:23:52 +0000231 unsigned char value;
232#endif
233 }
234cma_mb_reg;
235
236extern __inline__ unsigned char
237cma_mb_reg_read(volatile cma_mb_reg *reg)
238{
239 unsigned char data = reg->value;
240 __asm__ __volatile__ ("eieio" : : : "memory");
241 return data;
242}
243
244extern __inline__ void
245cma_mb_reg_write(volatile cma_mb_reg *reg, unsigned char data)
246{
247 reg->value = data;
248 __asm__ __volatile__ ("eieio" : : : "memory");
249}
250
251#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
252
253/* MK48T02 RTC registers */
254typedef
255 struct {
256 cma_mb_reg sram[2040];/* Battery-Backed SRAM */
257 cma_mb_reg clk_ctl; /* Clock Control Register */
258 cma_mb_reg clk_sec; /* Clock Seconds Register */
259 cma_mb_reg clk_min; /* Clock Minutes Register */
260 cma_mb_reg clk_hour; /* Clock Hour Register */
261 cma_mb_reg clk_day; /* Clock Day Register */
262 cma_mb_reg clk_date; /* Clock Date Register */
263 cma_mb_reg clk_month; /* Clock Month Register */
264 cma_mb_reg clk_year; /* Clock Year Register */
265 }
266cma_mb_rtc;
267
268#endif
269
270#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
271
272/* ST16C522 Serial I/O */
273typedef
274 struct {
275 cma_mb_reg ser_rhr; /* Receive Holding Register (R, DLAB=0) */
276 cma_mb_reg ser_ier; /* Interrupt Enable Register (R/W, DLAB=0) */
277 cma_mb_reg ser_isr; /* Interrupt Status Register (R) */
278 cma_mb_reg ser_lcr; /* Line Control Register (R/W) */
279 cma_mb_reg ser_mcr; /* Modem Control Register (R/W) */
280 cma_mb_reg ser_lsr; /* Line Status Register (R) */
281 cma_mb_reg ser_msr; /* Modem Status Register (R/W) */
282 cma_mb_reg ser_spr; /* Scratch Pad Register (R/W) */
283 }
284cma_mb_serial;
285
286#define ser_thr ser_rhr /* Transmit Holding Register (W, DLAB=0) */
287#define ser_brl ser_rhr /* Baud Rate Divisor Low Byte (R/W, DLAB=1) */
288#define ser_brh ser_ier /* Baud Rate Divisor High Byte (R/W, DLAB=1) */
289#define ser_fcr ser_isr /* FIFO Control Register (W) */
290#define ser_nop ser_lsr /* No Operation (W) */
291
292/* ST16C522 Parallel I/O */
293typedef
294 struct {
295 cma_mb_reg par_rdr; /* Port Read Data Register (R) */
296 cma_mb_reg par_sr; /* Status Register (R) */
297 cma_mb_reg par_cmd; /* Command Register (R) */
298 }
299cma_mb_parallel;
300
301#define par_wdr par_rdr /* Port Write Data Register (W) */
302#define par_ios par_sr /* I/O Select Register (W) */
303#define par_ctl par_cmd /* Control Register (W) */
304
305#endif
306
307#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302)
308
309/* HT6542B PS/2 Keyboard/Mouse Controller */
310typedef
311 struct {
312 cma_mb_reg kbm_rdr; /* Read Data Register (R) */
313 cma_mb_reg kbm_sr; /* Status Register (R) */
314 }
315cma_mb_kbm;
316
317#define kbm_wdr kbm_rdr /* Write Data Register (W) */
318#define kbm_cmd kbm_sr /* Command Register (W) */
319
320#endif
321
322#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
323
324/* HD44780 LCD Display */
325typedef
326 struct {
327 cma_mb_reg lcd_ccr; /* Current Character Register (R/W) */
328 cma_mb_reg lcd_bsr; /* Busy Status Register (R) */
329 }
330cma_mb_lcd;
331
332#define lcd_cmd lcd_bsr /* Command Register (W) */
333
334#endif
335
336/* 8-Position Configuration Switch */
337typedef
338 struct {
339 cma_mb_reg dip_val; /* Dip Switch value (R) */
340 }
341cma_mb_dipsw;
342
343#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
344
345/* V360EPC PCI Bridge */
346typedef
347 struct {
wdenkda93ed82004-09-29 11:02:56 +0000348#if __BYTE_ORDER == __LITTLE_ENDIAN
wdenk1d589e32001-01-20 01:23:52 +0000349 unsigned short v3_pci_vendor; /* 0x00 */
350 unsigned short v3_pci_device;
351 unsigned short v3_pci_cmd; /* 0x04 */
352 unsigned short v3_pci_stat;
353 unsigned long v3_pci_cc_rev; /* 0x08 */
354 unsigned long v3_pci_hdr_cfg; /* 0x0c */
355 unsigned long v3_pci_io_base; /* 0x10 */
356 unsigned long v3_pci_base0; /* 0x14 */
357 unsigned long v3_pci_base1; /* 0x18 */
358 unsigned long reserved1[4]; /* 0x1c */
359 unsigned short v3_pci_sub_vendor; /* 0x2c */
360 unsigned short v3_pci_sub_id;
361 unsigned long v3_pci_rom; /* 0x30 */
362 unsigned long reserved2[2]; /* 0x34 */
363 unsigned long v3_pci_bparam; /* 0x3c */
364 unsigned long v3_pci_map0; /* 0x40 */
365 unsigned long v3_pci_map1; /* 0x44 */
366 unsigned long v3_pci_int_stat; /* 0x48 */
367 unsigned long v3_pci_int_cfg; /* 0x4c */
368 unsigned long reserved3[1]; /* 0x50 */
369 unsigned long v3_lb_base0; /* 0x54 */
370 unsigned long v3_lb_base1; /* 0x58 */
371 unsigned short reserved4; /* 0x5c */
372 unsigned short v3_lb_map0;
373 unsigned short reserved5; /* 0x60 */
374 unsigned short v3_lb_map1;
375 unsigned short v3_lb_base2; /* 0x64 */
376 unsigned short v3_lb_map2;
377 unsigned long v3_lb_size; /* 0x68 */
378 unsigned short reserved6; /* 0x6c */
379 unsigned short v3_lb_io_base;
380 unsigned short v3_fifo_cfg; /* 0x70 */
381 unsigned short v3_fifo_priority;
382 unsigned short v3_fifo_stat; /* 0x74 */
383 unsigned char v3_lb_istat;
384 unsigned char v3_lb_imask;
385 unsigned short v3_system; /* 0x78 */
386 unsigned short v3_lb_cfg;
387 unsigned short v3_pci_cfg; /* 0x7c */
388 unsigned short reserved7;
389 unsigned long v3_dma_pci_addr0; /* 0x80 */
390 unsigned long v3_dma_local_addr0; /* 0x84 */
391 unsigned long v3_dma_length0:24; /* 0x88 */
392 unsigned long v3_dma_csr0:8;
393 unsigned long v3_dma_ctlb_adr0; /* 0x8c */
394 unsigned long v3_dma_pci_addr1; /* 0x90 */
395 unsigned long v3_dma_local_addr1; /* 0x94 */
396 unsigned long v3_dma_length1:24; /* 0x98 */
397 unsigned long v3_dma_csr1:8;
398 unsigned long v3_dma_ctlb_adr1; /* 0x9c */
399 unsigned long v3_i20_mups[8]; /* 0xa0 */
400 unsigned char v3_mail_data0; /* 0xc0 */
401 unsigned char v3_mail_data1;
402 unsigned char v3_mail_data2;
403 unsigned char v3_mail_data3;
404 unsigned char v3_mail_data4; /* 0xc4 */
405 unsigned char v3_mail_data5;
406 unsigned char v3_mail_data6;
407 unsigned char v3_mail_data7;
408 unsigned char v3_mail_data8; /* 0xc8 */
409 unsigned char v3_mail_data9;
410 unsigned char v3_mail_data10;
411 unsigned char v3_mail_data11;
412 unsigned char v3_mail_data12; /* 0xcc */
413 unsigned char v3_mail_data13;
414 unsigned char v3_mail_data14;
415 unsigned char v3_mail_data15;
416 unsigned short v3_pci_mail_iewr; /* 0xd0 */
417 unsigned short v3_pci_mail_ierd;
418 unsigned short v3_lb_mail_iewr; /* 0xd4 */
419 unsigned short v3_lb_mail_ierd;
420 unsigned short v3_mail_wr_stat; /* 0xd8 */
421 unsigned short v3_mail_rd_stat;
422 unsigned long v3_qba_map; /* 0xdc */
423 unsigned long v3_dma_delay:8; /* 0xe0 */
424 unsigned long reserved8:24;
425 unsigned long reserved9[7]; /* 0xe4 */
426#endif
wdenkda93ed82004-09-29 11:02:56 +0000427#if __BYTE_ORDER == __BIG_ENDIAN
wdenk1d589e32001-01-20 01:23:52 +0000428 unsigned short v3_pci_device; /* 0x00 */
429 unsigned short v3_pci_vendor;
430 unsigned short v3_pci_stat; /* 0x04 */
431 unsigned short v3_pci_cmd;
432 unsigned long v3_pci_cc_rev; /* 0x08 */
433 unsigned long v3_pci_hdr_cfg; /* 0x0c */
434 unsigned long v3_pci_io_base; /* 0x10 */
435 unsigned long v3_pci_base0; /* 0x14 */
436 unsigned long v3_pci_base1; /* 0x18 */
437 unsigned long reserved1[4]; /* 0x1c */
438 unsigned short v3_pci_sub_id; /* 0x2c */
439 unsigned short v3_pci_sub_vendor;
440 unsigned long v3_pci_rom; /* 0x30 */
441 unsigned long reserved2[2]; /* 0x34 */
442 unsigned long v3_pci_bparam; /* 0x3c */
443 unsigned long v3_pci_map0; /* 0x40 */
444 unsigned long v3_pci_map1; /* 0x44 */
445 unsigned long v3_pci_int_stat; /* 0x48 */
446 unsigned long v3_pci_int_cfg; /* 0x4c */
447 unsigned long reserved3; /* 0x50 */
448 unsigned long v3_lb_base0; /* 0x54 */
449 unsigned long v3_lb_base1; /* 0x58 */
450 unsigned short v3_lb_map0; /* 0x5c */
451 unsigned short reserved4;
452 unsigned short v3_lb_map1; /* 0x60 */
453 unsigned short reserved5;
454 unsigned short v3_lb_map2; /* 0x64 */
455 unsigned short v3_lb_base2;
456 unsigned long v3_lb_size; /* 0x68 */
457 unsigned short v3_lb_io_base; /* 0x6c */
458 unsigned short reserved6;
459 unsigned short v3_fifo_priority; /* 0x70 */
460 unsigned short v3_fifo_cfg;
461 unsigned char v3_lb_imask; /* 0x74 */
462 unsigned char v3_lb_istat;
463 unsigned short v3_fifo_stat;
464 unsigned short v3_lb_cfg; /* 0x78 */
465 unsigned short v3_system;
466 unsigned short reserved7; /* 0x7c */
467 unsigned short v3_pci_cfg;
468 unsigned long v3_dma_pci_addr0; /* 0x80 */
469 unsigned long v3_dma_local_addr0; /* 0x84 */
470 unsigned long v3_dma_csr0:8; /* 0x88 */
471 unsigned long v3_dma_length0:24;
472 unsigned long v3_dma_ctlb_adr0; /* 0x8c */
473 unsigned long v3_dma_pci_addr1; /* 0x90 */
474 unsigned long v3_dma_local_addr1; /* 0x94 */
475 unsigned long v3_dma_csr1:8; /* 0x98 */
476 unsigned long v3_dma_length1:24;
477 unsigned long v3_dma_ctlb_adr1; /* 0x9c */
478 unsigned long v3_i20_mups[8]; /* 0xa0 */
479 unsigned char v3_mail_data3; /* 0xc0 */
480 unsigned char v3_mail_data2;
481 unsigned char v3_mail_data1;
482 unsigned char v3_mail_data0;
483 unsigned char v3_mail_data7; /* 0xc4 */
484 unsigned char v3_mail_data6;
485 unsigned char v3_mail_data5;
486 unsigned char v3_mail_data4;
487 unsigned char v3_mail_data11; /* 0xc8 */
488 unsigned char v3_mail_data10;
489 unsigned char v3_mail_data9;
490 unsigned char v3_mail_data8;
491 unsigned char v3_mail_data15; /* 0xcc */
492 unsigned char v3_mail_data14;
493 unsigned char v3_mail_data13;
494 unsigned char v3_mail_data12;
495 unsigned short v3_pci_mail_ierd; /* 0xd0 */
496 unsigned short v3_pci_mail_iewr;
497 unsigned short v3_lb_mail_ierd; /* 0xd4 */
498 unsigned short v3_lb_mail_iewr;
499 unsigned short v3_mail_rd_stat; /* 0xd8 */
500 unsigned short v3_mail_wr_stat;
501 unsigned long v3_qba_map; /* 0xdc */
502 unsigned long reserved8:24; /* 0xe0 */
503 unsigned long v3_dma_delay:8;
504 unsigned long reserved9[7]; /* 0xe4 */
505#endif
506 } /* 0x100 */
507cma_mb_v360epc;
508
509#endif
510
511#endif /* __ASSEMBLY__ */
512
513#endif /* _COGENT_MB_H */